Peter Maydell
ecba223da6
target-arm queue:
* Don't require 'virt' board to be compiled in for ACPI GHES code
* docs: Document which architecture extensions we emulate
* Fix bugs in M-profile FPCXT_NS accesses
* First slice of MVE patches
* Implement MTE3
* docs/system: arm: Add nRF boards description
-----BEGIN PGP SIGNATURE-----
iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmDUj7QZHHBldGVyLm1h
eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3jffEACAqLxGeZ9ybE9JOr6Nryxf
fXCO6h2/3OR9jlixhMXMgksbjC82Z02kE/ywBUQ1OpgxlGiRcRBWNrhFBdiATXTS
KhFiD+KZwiguTXgSm4VrFFWru7UOyj+kQIiNwEHYRs6iG/zZYamdQilK9gvWqR+M
smXf6/tj+U5s9y53ZFSdCnZMOsdNcrwEN8VgMUwxDlB2/HsM9bg2eymSs5C4lJXF
/H3ZjjmHUzeYUma5NXlDORu9ri2OxRYdXxLHeHwEmw1MZE8J8kwbnbGYdpC490o4
nCIqJJGNq9K+jw6oFWKitzjOlvZBzx4+vbX0g0BCRd3g+oviBCfKazOSBrQM1AuI
iGSsdfuaNMcv07O+pAE/WPrqtR2hvTVVXX4j9f9rTDNyqNjja7t3hnsyW9+KyQrZ
Rl3Ha5YBH+Upe1TF6MV7gE4z07vjjD6Xem5HNHBcOP91WnK/sw1yOtFfl6cQlLcr
ukUhHu+Il5FErSityZfgx25hI2Cin2oBgnleAbe5DKaWFt5cMPwGpb0GnIjOeilr
O7KzC8LejTPssBRYndpvxvhgfFTXsws4bxMal/RBLTFuLAg7D/hrTBTUzxSnq+hw
b9Keewj646vfEY+g/B/B02kT8NVnial5MOqkqL1I87r2BNOjbY6R7T5UBDYl8kP8
Ph4lpz+ECQL5N04t9MhwhA==
=6zaW
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210624' into staging
target-arm queue:
* Don't require 'virt' board to be compiled in for ACPI GHES code
* docs: Document which architecture extensions we emulate
* Fix bugs in M-profile FPCXT_NS accesses
* First slice of MVE patches
* Implement MTE3
* docs/system: arm: Add nRF boards description
# gpg: Signature made Thu 24 Jun 2021 14:59:16 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210624: (57 commits)
docs/system: arm: Add nRF boards description
target/arm: Implement MTE3
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
target/arm: Implement MVE VADDV
target/arm: Implement MVE VHCADD
target/arm: Implement MVE VCADD
target/arm: Implement MVE VADC, VSBC
target/arm: Implement MVE VRHADD
target/arm: Implement MVE VQDMULL (vector)
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
target/arm: Implement MVE VQDMLADH and VQRDMLADH
target/arm: Implement MVE VRSHL
target/arm: Implement MVE VSHL insn
target/arm: Implement MVE VQRSHL
target/arm: Implement MVE VQSHL (vector)
target/arm: Implement MVE VQADD, VQSUB (vector)
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
target/arm: Implement MVE VQDMULL scalar
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
target/arm: Implement MVE VQADD and VQSUB
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-24 15:00:34 +01:00
..
2021-06-18 12:21:22 -05:00
2021-06-19 08:51:11 -07:00
2021-06-21 05:49:01 +02:00
2021-06-24 15:00:34 +01:00
2021-06-24 09:31:26 +01:00
2021-06-17 14:11:06 -04:00
2021-06-17 15:43:26 +01:00
2021-06-24 15:00:34 +01:00
2021-06-21 05:49:01 +02:00
2021-06-21 08:48:21 +02:00