qemu/target/riscv/insn_trans/trans_xventanacondops.c.inc
Philipp Tomsich 0d429bd243 target/riscv: Add XVentanaCondOps custom extension
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf

This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16 12:24:18 +10:00

40 lines
1.2 KiB
C++

/*
* RISC-V translation routines for the XVentanaCondOps extension.
*
* Copyright (c) 2021-2022 VRULL GmbH.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
{
return gen_vt_condmask(ctx, a, TCG_COND_NE);
}
static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
{
return gen_vt_condmask(ctx, a, TCG_COND_EQ);
}