f008a2d218
We should call decode_save_opc() for all relevant instructions which
can potentially generate a virtual instruction fault or a guest page
fault because generating transformed instruction upon guest page fault
expects opcode to be available. Without this, hypervisor will see
transformed instruction as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.
Fixes: a9814e3e08 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
79 lines
2.1 KiB
C++
79 lines
2.1 KiB
C++
/*
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* RISC-V translation routines for the Svinval Standard Instruction Set.
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*
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* Copyright (c) 2020-2022 PLCT lab
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_SVINVAL(ctx) do { \
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if (!ctx->cfg_ptr->ext_svinval) { \
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return false; \
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} \
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} while (0)
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static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
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{
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REQUIRE_SVINVAL(ctx);
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/* Do the same as sfence.vma currently */
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REQUIRE_EXT(ctx, RVS);
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#ifndef CONFIG_USER_ONLY
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decode_save_opc(ctx);
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gen_helper_tlb_flush(cpu_env);
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return true;
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#endif
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return false;
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}
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static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
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{
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REQUIRE_SVINVAL(ctx);
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REQUIRE_EXT(ctx, RVS);
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/* Do nothing currently */
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return true;
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}
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static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
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{
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REQUIRE_SVINVAL(ctx);
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REQUIRE_EXT(ctx, RVS);
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/* Do nothing currently */
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return true;
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}
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static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
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{
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REQUIRE_SVINVAL(ctx);
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/* Do the same as hfence.vvma currently */
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REQUIRE_EXT(ctx, RVH);
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#ifndef CONFIG_USER_ONLY
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decode_save_opc(ctx);
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gen_helper_hyp_tlb_flush(cpu_env);
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return true;
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#endif
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return false;
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}
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static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
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{
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REQUIRE_SVINVAL(ctx);
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/* Do the same as hfence.gvma currently */
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REQUIRE_EXT(ctx, RVH);
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#ifndef CONFIG_USER_ONLY
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decode_save_opc(ctx);
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gen_helper_hyp_gvma_tlb_flush(cpu_env);
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return true;
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#endif
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return false;
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}
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