Eric Johnson 36c6711bbe target-mips: allow microMIPS SWP and SDP to have RD equal to BASE ... The microMIPS SWP and SDP instructions do not modify GPRs. So their behavior is well defined when RD equals BASE. The MIPS Architecture Verification Programs (AVPs) check that they work as expected. This is required for AVPs to pass. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2012-08-27 22:18:02 +02:00
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cpu-qom.h	target-mips: QOM'ify CPU	2012-04-30 11:32:13 +02:00
cpu.c	target-mips: Start QOM'ifying CPU init	2012-04-30 11:32:13 +02:00
cpu.h	Kill off cpu_state_reset()	2012-06-04 23:00:45 +02:00
helper.c	target-mips: Use cpu_reset() in do_interrupt()	2012-06-04 23:00:43 +02:00
helper.h	target-mips: Add compiler attribute to some functions which don't return	2012-03-24 13:02:43 +00:00
machine.c	target-mips: Don't overuse CPUState	2012-03-14 22:20:25 +01:00
Makefile.objs	build: move other target-*/ objects to nested Makefile.objs	2012-06-07 09:21:11 +02:00
mips-defs.h
op_helper.c	target-mips: Fix some helper functions (VR54xx multiplication)	2012-08-24 01:03:26 +02:00
TODO	Replace Qemu by QEMU in internal documentation	2012-04-07 13:58:25 +00:00
translate_init.c	mips: Default to using one VPE and one TC.	2011-09-06 11:09:39 +02:00
translate.c	target-mips: allow microMIPS SWP and SDP to have RD equal to BASE	2012-08-27 22:18:02 +02:00