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Michael Rolnik 5718cef05a target/avr: Add instruction translation - Bit and Bit-test Instructions 
This includes:
    - LSR, ROR
    - ASR
    - SWAP
    - SBI, CBI
    - BST, BLD
    - BSET, BCLR

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-15-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-07-11 11:02:05 +02:00
..
cpu-param.h
…
cpu-qom.h
…
cpu.c
target/avr: Add definitions of AVR core types
2020-07-10 17:58:32 +02:00
cpu.h
target/avr: Introduce enumeration AVRFeature
2020-07-10 17:58:32 +02:00
gdbstub.c
target/avr: CPU class: Add GDB support
2020-07-10 17:58:32 +02:00
helper.c
target/avr: Add instruction helpers
2020-07-11 11:02:05 +02:00
helper.h
target/avr: Add instruction helpers
2020-07-11 11:02:05 +02:00
insn.decode
target/avr: Add instruction translation - Bit and Bit-test Instructions
2020-07-11 11:02:05 +02:00
machine.c
…
translate.c
target/avr: Add instruction translation - Bit and Bit-test Instructions
2020-07-11 11:02:05 +02:00