fcbd8018e6
This is based on mcf_fec.c FEC implementation for Coldfire
* A generic PHY was added (borrowwed from LAN9118)
* The buffer management is also modified as buffers are
slightly different between Coldfire and i.MX
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: fb314f8a120aa49f8f6ad886f312c649b484fb5a.1441057361.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
/*
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* i.MX Fast Ethernet Controller emulation.
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*
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* Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
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*
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* Based on Coldfire Fast Ethernet Controller emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef IMX_FEC_H
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#define IMX_FEC_H
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#define TYPE_IMX_FEC "imx.fec"
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#define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC)
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#include "hw/sysbus.h"
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#include "net/net.h"
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#define FEC_MAX_FRAME_SIZE 2032
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#define FEC_INT_HB (1 << 31)
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#define FEC_INT_BABR (1 << 30)
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#define FEC_INT_BABT (1 << 29)
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#define FEC_INT_GRA (1 << 28)
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#define FEC_INT_TXF (1 << 27)
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#define FEC_INT_TXB (1 << 26)
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#define FEC_INT_RXF (1 << 25)
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#define FEC_INT_RXB (1 << 24)
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#define FEC_INT_MII (1 << 23)
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#define FEC_INT_EBERR (1 << 22)
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#define FEC_INT_LC (1 << 21)
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#define FEC_INT_RL (1 << 20)
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#define FEC_INT_UN (1 << 19)
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#define FEC_EN 2
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#define FEC_RESET 1
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/* Buffer Descriptor. */
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typedef struct {
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uint16_t length;
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uint16_t flags;
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uint32_t data;
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} IMXFECBufDesc;
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#define FEC_BD_R (1 << 15)
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#define FEC_BD_E (1 << 15)
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#define FEC_BD_O1 (1 << 14)
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#define FEC_BD_W (1 << 13)
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#define FEC_BD_O2 (1 << 12)
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#define FEC_BD_L (1 << 11)
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#define FEC_BD_TC (1 << 10)
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#define FEC_BD_ABC (1 << 9)
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#define FEC_BD_M (1 << 8)
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#define FEC_BD_BC (1 << 7)
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#define FEC_BD_MC (1 << 6)
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#define FEC_BD_LG (1 << 5)
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#define FEC_BD_NO (1 << 4)
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#define FEC_BD_CR (1 << 2)
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#define FEC_BD_OV (1 << 1)
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#define FEC_BD_TR (1 << 0)
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typedef struct IMXFECState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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NICState *nic;
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NICConf conf;
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qemu_irq irq;
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MemoryRegion iomem;
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uint32_t irq_state;
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uint32_t eir;
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uint32_t eimr;
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uint32_t rx_enabled;
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uint32_t rx_descriptor;
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uint32_t tx_descriptor;
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uint32_t ecr;
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uint32_t mmfr;
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uint32_t mscr;
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uint32_t mibc;
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uint32_t rcr;
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uint32_t tcr;
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uint32_t tfwr;
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uint32_t frsr;
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uint32_t erdsr;
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uint32_t etdsr;
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uint32_t emrbr;
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uint32_t miigsk_cfgr;
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uint32_t miigsk_enr;
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uint32_t phy_status;
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uint32_t phy_control;
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uint32_t phy_advertise;
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uint32_t phy_int;
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uint32_t phy_int_mask;
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} IMXFECState;
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#endif
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