56f6e31e7b
This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
89 lines
2.7 KiB
C
89 lines
2.7 KiB
C
/*
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* Microchip PolarFire SoC machine interface
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_MICROCHIP_PFSOC_H
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#define HW_MICROCHIP_PFSOC_H
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typedef struct MicrochipPFSoCState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CPUClusterState e_cluster;
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CPUClusterState u_cluster;
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RISCVHartArrayState e_cpus;
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RISCVHartArrayState u_cpus;
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DeviceState *plic;
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} MicrochipPFSoCState;
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#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
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#define MICROCHIP_PFSOC(obj) \
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OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
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typedef struct MicrochipIcicleKitState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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MicrochipPFSoCState soc;
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} MicrochipIcicleKitState;
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#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
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MACHINE_TYPE_NAME("microchip-icicle-kit")
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#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
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OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
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TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
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enum {
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MICROCHIP_PFSOC_DEBUG,
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MICROCHIP_PFSOC_E51_DTIM,
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MICROCHIP_PFSOC_BUSERR_UNIT0,
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MICROCHIP_PFSOC_BUSERR_UNIT1,
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MICROCHIP_PFSOC_BUSERR_UNIT2,
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MICROCHIP_PFSOC_BUSERR_UNIT3,
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MICROCHIP_PFSOC_BUSERR_UNIT4,
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MICROCHIP_PFSOC_CLINT,
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MICROCHIP_PFSOC_L2CC,
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MICROCHIP_PFSOC_L2LIM,
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MICROCHIP_PFSOC_PLIC,
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MICROCHIP_PFSOC_SYSREG,
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MICROCHIP_PFSOC_MPUCFG,
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MICROCHIP_PFSOC_ENVM_CFG,
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MICROCHIP_PFSOC_ENVM_DATA,
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MICROCHIP_PFSOC_IOSCB_CFG,
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MICROCHIP_PFSOC_DRAM,
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};
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#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
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#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
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#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
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#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
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#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
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#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
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#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
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#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
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#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
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#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
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#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
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#endif /* HW_MICROCHIP_PFSOC_H */
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