4b7f956862
GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC. (Note that the ast2400 controller only goes up to group AB). A set has four groups (except set AC which only has one) and is referred to by the groups it is composed of (eg ABCD,EFGH,...,YZAAAB). Each set is accessed and controlled by a bank of 14 registers. These registers operate on a per pin level where each bit in the register corresponds to a pin, except for the command source registers. The command source registers operate on a per group level where bits 24, 16, 8 and 0 correspond to each group in the set. eg. registers for set ABCD: |D7...D0|C7...C0|B7...B0|A7...A0| <- GPIOs |31...24|23...16|15....8|7.....0| <- bit position Note that there are a couple of groups that only have 4 pins. There are two ways that this model deviates from the behaviour of the actual controller: (1) The only control source driving the GPIO pins in the model is the ARM model (as there currently aren't models for the LPC or Coprocessor). (2) None of the registers in the model are reset tolerant (needs integration with the watchdog). Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Tested-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-2-clg@kaod.org [clg: fixed missing header files made use of HWADDR_PRIx to fix compilation on windows ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
101 lines
2.6 KiB
C
101 lines
2.6 KiB
C
/*
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* ASPEED GPIO Controller
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*
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* Copyright (C) 2017-2018 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_GPIO_H
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#define ASPEED_GPIO_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_GPIO "aspeed.gpio"
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#define ASPEED_GPIO(obj) OBJECT_CHECK(AspeedGPIOState, (obj), TYPE_ASPEED_GPIO)
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#define ASPEED_GPIO_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedGPIOClass, (klass), TYPE_ASPEED_GPIO)
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#define ASPEED_GPIO_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedGPIOClass, (obj), TYPE_ASPEED_GPIO)
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#define ASPEED_GPIO_MAX_NR_SETS 8
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#define ASPEED_REGS_PER_BANK 14
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#define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS)
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#define ASPEED_GPIO_NR_PINS 228
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#define ASPEED_GROUPS_PER_SET 4
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#define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
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#define ASPEED_CHARS_PER_GROUP_LABEL 4
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typedef struct GPIOSets GPIOSets;
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typedef struct GPIOSetProperties {
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uint32_t input;
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uint32_t output;
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char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
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} GPIOSetProperties;
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enum GPIORegType {
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gpio_not_a_reg,
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gpio_reg_data_value,
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gpio_reg_direction,
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gpio_reg_int_enable,
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gpio_reg_int_sens_0,
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gpio_reg_int_sens_1,
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gpio_reg_int_sens_2,
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gpio_reg_int_status,
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gpio_reg_reset_tolerant,
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gpio_reg_debounce_1,
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gpio_reg_debounce_2,
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gpio_reg_cmd_source_0,
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gpio_reg_cmd_source_1,
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gpio_reg_data_read,
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gpio_reg_input_mask,
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};
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typedef struct AspeedGPIOReg {
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uint16_t set_idx;
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enum GPIORegType type;
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} AspeedGPIOReg;
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typedef struct AspeedGPIOClass {
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SysBusDevice parent_obj;
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const GPIOSetProperties *props;
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uint32_t nr_gpio_pins;
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uint32_t nr_gpio_sets;
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uint32_t gap;
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const AspeedGPIOReg *reg_table;
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} AspeedGPIOClass;
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typedef struct AspeedGPIOState {
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/* <private> */
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SysBusDevice parent;
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/*< public >*/
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MemoryRegion iomem;
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int pending;
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qemu_irq irq;
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qemu_irq gpios[ASPEED_GPIO_NR_PINS];
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/* Parallel GPIO Registers */
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uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
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struct GPIOSets {
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uint32_t data_value; /* Reflects pin values */
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uint32_t data_read; /* Contains last value written to data value */
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uint32_t direction;
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uint32_t int_enable;
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uint32_t int_sens_0;
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uint32_t int_sens_1;
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uint32_t int_sens_2;
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uint32_t int_status;
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uint32_t reset_tol;
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uint32_t cmd_source_0;
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uint32_t cmd_source_1;
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uint32_t debounce_1;
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uint32_t debounce_2;
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uint32_t input_mask;
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} sets[ASPEED_GPIO_MAX_NR_SETS];
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} AspeedGPIOState;
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#endif /* _ASPEED_GPIO_H_ */
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