Bin Meng 56118ee88d target/riscv: Make csr_ops[CSR_TABLE_SIZE] external ...

In preparation to generate the CSR register list for GDB stub
dynamically, change csr_ops[] to non-static so that it can be
referenced externally.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-01-16 10:57:21 -08:00

..

alpha

…

arm

target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns

2021-01-12 21:19:02 +00:00

avr

tcg: Make tb arg to synchronize_from_tb const

2021-01-07 05:09:41 -10:00

cris

…

hppa

tcg: Make tb arg to synchronize_from_tb const

2021-01-07 05:09:41 -10:00

i386

target/i386: Use X86Seg enum for segment registers

2021-01-12 17:05:10 +01:00

lm32

…

m68k

…

microblaze

tcg: Make tb arg to synchronize_from_tb const

2021-01-07 05:09:41 -10:00

mips

target/mips: Remove vendor specific CPU definitions

2021-01-14 17:13:54 +01:00

moxie

…

nios2

…

openrisc

…

ppc

…

riscv

target/riscv: Make csr_ops[CSR_TABLE_SIZE] external

2021-01-16 10:57:21 -08:00

rx

tcg: Make tb arg to synchronize_from_tb const

2021-01-07 05:09:41 -10:00

s390x

Remove superfluous timer_del() calls

2021-01-08 15:13:38 +00:00

sh4

tcg: Make tb arg to synchronize_from_tb const

2021-01-07 05:09:41 -10:00

sparc

tcg: Make tb arg to synchronize_from_tb const

2021-01-07 05:09:41 -10:00

tilegx

…

tricore

tcg: Make tb arg to synchronize_from_tb const

2021-01-07 05:09:41 -10:00

unicore32

…

xtensa

…

meson.build

…