Alistair Francis ec2c62dacc hw/riscv: boot: Reduce FDT address alignment constraints ... We previously stored the device tree at a 16MB alignment from the end of memory (or 3GB). This means we need at least 16MB of memory to be able to do this. We don't actually need the FDT to be 16MB aligned, so let's drop it down to 2MB so that we can support systems with less memory, while also allowing FDT size expansion. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20220608062015.317894-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-07-03 10:03:20 +10:00
..
boot.c	hw/riscv: boot: Reduce FDT address alignment constraints	2022-07-03 10:03:20 +10:00
Kconfig
meson.build
microchip_pfsoc.c
numa.c
opentitan.c
riscv_hart.c
shakti_c.c
sifive_e.c
sifive_u.c	hw/riscv/sifive_u: Resolve redundant property accessors	2022-05-24 10:38:50 +10:00
spike.c
virt.c	hw/riscv: virt: Generate fw_cfg DT node correctly	2022-06-10 09:31:42 +10:00