d572bcb222
While the 8-bit input elements are sequential in the input vector,
the 32-bit output elements are not sequential in the output matrix.
Do not attempt to compute 2 32-bit outputs at the same time.
Cc: qemu-stable@nongnu.org
Fixes: 23a5e3859f ("target/arm: Implement SME integer outer product")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240305163931.242795-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
#include <stdio.h>
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#include <string.h>
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int main()
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{
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static const long cmp[4][4] = {
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{ 110, 134, 158, 182 },
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{ 390, 478, 566, 654 },
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{ 670, 822, 974, 1126 },
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{ 950, 1166, 1382, 1598 }
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};
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long dst[4][4];
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long *tmp = &dst[0][0];
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long svl;
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/* Validate that we have a wide enough vector for 4 elements. */
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asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
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if (svl < 32) {
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return 0;
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}
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asm volatile(
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"smstart\n\t"
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"index z0.h, #0, #1\n\t"
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"movprfx z1, z0\n\t"
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"add z1.h, z1.h, #16\n\t"
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"ptrue p0.b\n\t"
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"smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t"
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"ptrue p0.d, vl4\n\t"
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"mov w12, #0\n\t"
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"st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
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"add %0, %0, #32\n\t"
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"st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
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"mov w12, #2\n\t"
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"add %0, %0, #32\n\t"
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"st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
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"add %0, %0, #32\n\t"
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"st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
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"smstop"
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: "+r"(tmp) : : "memory");
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if (memcmp(cmp, dst, sizeof(dst)) == 0) {
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return 0;
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}
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/* See above for correct results. */
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for (int i = 0; i < 4; ++i) {
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for (int j = 0; j < 4; ++j) {
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printf("%6ld", dst[i][j]);
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}
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printf("\n");
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}
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return 1;
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}
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