qemu/target
Max Filippov 553e53b442 target/xtensa: fix OOB TLB entry access
r[id]tlb[01], [iw][id]tlb opcodes use TLB way index passed in a register
by the guest. The host uses 3 bits of the index for ITLB indexing and 4
bits for DTLB, but there's only 7 entries in the ITLB array and 10 in
the DTLB array, so a malicious guest may trigger out-of-bound access to
these arrays.

Change split_tlb_entry_spec return type to bool to indicate whether TLB
way passed to it is valid. Change get_tlb_entry to return NULL in case
invalid TLB way is requested. Add assertion to xtensa_tlb_get_entry that
requested TLB way and entry indices are valid. Add checks to the
[rwi]tlb helpers that requested TLB way is valid and return 0 or do
nothing when it's not.

Cc: qemu-stable@nongnu.org
Fixes: b67ea0cd74 ("target-xtensa: implement memory protection options")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20231215120307.545381-1-jcmvbkbc@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 604927e357)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-27 18:04:54 +03:00
..
alpha hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
arm target/arm: Disable SME if SVE is disabled 2023-12-04 13:34:16 +00:00
avr hw/avr/atmega: Fix wrong initial value of stack pointer 2023-11-28 14:27:12 +01:00
cris hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
hexagon target/hexagon/idef-parser/prepare: use env to invoke bash 2023-11-28 14:26:37 +01:00
hppa target/hppa: Fix IOR and ISR on error in probe 2024-01-17 10:32:47 +03:00
i386 target/i386: pcrel: store low bits of physical address in data[0] 2024-01-20 12:24:50 +03:00
loongarch hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
m68k hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
microblaze target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
mips target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
nios2 target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
openrisc hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
ppc target/ppc: Fix bugs in VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros 2023-11-21 08:39:58 +01:00
riscv target/riscv: Fix mcycle/minstret increment behavior 2024-01-08 19:24:31 +03:00
rx hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
s390x target/s390x: Fix LAE setting a wrong access register 2024-01-13 11:20:14 +03:00
sh4 sh4: Coding style: Remove tabs 2023-12-04 15:12:57 +01:00
sparc target/sparc: Fix RETURN 2023-11-14 10:40:54 -08:00
tricore hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
xtensa target/xtensa: fix OOB TLB entry access 2024-01-27 18:04:54 +03:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00