62be393423
Add support for emulating the Xilinx AXI Root Port Bridge for PCI Express as described by Xilinx' PG055 document. This is a PCIe controller that can be used with certain series of Xilinx FPGAs, and is used on the MIPS Boston board which will make use of this code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [yongbok.kim@imgtec.com: removed returning on !level, updated IRQ connection with GPIO logic, moved xilinx_pcie_init() to boston.c replaced stw_le_p() with pci_set_word() and other cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
20 lines
569 B
Makefile
20 lines
569 B
Makefile
common-obj-y += pam.o
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# PPC devices
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common-obj-$(CONFIG_PREP_PCI) += prep.o
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common-obj-$(CONFIG_GRACKLE_PCI) += grackle.o
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# NewWorld PowerMac
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common-obj-$(CONFIG_UNIN_PCI) += uninorth.o
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# PowerPC E500 boards
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common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o
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# ARM devices
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common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
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common-obj-$(CONFIG_PCI_APB) += apb.o
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common-obj-$(CONFIG_FULONG) += bonito.o
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common-obj-$(CONFIG_PCI_PIIX) += piix.o
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common-obj-$(CONFIG_PCI_Q35) += q35.o
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common-obj-$(CONFIG_PCI_GENERIC) += gpex.o
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common-obj-$(CONFIG_PCI_XILINX) += xilinx-pcie.o
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