qemu/target-mips
Leon Alrae f93c3a8d0c target-mips: flush QEMU TLB when disabling 64-bit addressing
CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit
Kernel/Supervisor/User Segments. If bit is cleared an access to
corresponding segment should generate Address Error Exception.

However, the guest may still be able to access some pages belonging to
the disabled 64-bit segment because we forget to flush QEMU TLB.

This patch fixes it.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-11-24 11:01:03 +00:00
..
Makefile.objs
TODO
cpu-qom.h
cpu.c
cpu.h target-mips: flush QEMU TLB when disabling 64-bit addressing 2015-11-24 11:01:03 +00:00
dsp_helper.c
gdbstub.c
helper.c target-mips: Fix exceptions while UX=0 2015-11-24 11:01:03 +00:00
helper.h
kvm.c
kvm_mips.h
lmi_helper.c
machine.c
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c target-mips: flush QEMU TLB when disabling 64-bit addressing 2015-11-24 11:01:03 +00:00
translate.c target-mips: add SIGRIE instruction 2015-10-30 14:36:19 +00:00
translate_init.c