qemu/target
Richard Henderson 88e74b6122 target/microblaze: Collected fixes for env->iflags
There are several problems here that can result in soft lockup,
depending on exactly where an interrupt or exception is delivered:

Include BIMM_FLAG in IFLAGS_TB_MASK, since it needs to follow D_FLAG.
Ensure that iflags is 0 when entering an interrupt/exception handler.
Add mb_cpu_synchronize_from_tb to restore iflags from tb->flags.
The change to t_sync_flags is cosmetic, but makes the code clearer.

This fixes the reported regression in acceptance/replay_kernel.py.

Fixes: 683a247ed7 ("target/microblaze: Store "current" iflags in insn_start")
Tested-by: Thomas Huth <thuth@redhat.com>
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200904190842.2282109-2-richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-09-07 12:34:17 +02:00
..
alpha meson: target 2020-08-21 06:30:35 -04:00
arm arm: Fix typo in AARCH64_CPU_GET_CLASS definition 2020-09-02 07:29:25 -04:00
avr meson: target 2020-08-21 06:30:35 -04:00
cris target/cris: Remove superfluous breaks 2020-09-01 08:41:15 +02:00
hppa meson: target 2020-08-21 06:30:35 -04:00
i386 target/i386/sev: Plug memleak in sev_read_file_base64 2020-09-02 07:30:26 -04:00
lm32 meson: target 2020-08-21 06:30:35 -04:00
m68k meson: target 2020-08-21 06:30:35 -04:00
microblaze target/microblaze: Collected fixes for env->iflags 2020-09-07 12:34:17 +02:00
mips meson: target 2020-08-21 06:30:35 -04:00
moxie meson: target 2020-08-21 06:30:35 -04:00
nios2 meson: target 2020-08-21 06:30:35 -04:00
openrisc meson: target 2020-08-21 06:30:35 -04:00
ppc target/ppc: Remove superfluous breaks 2020-09-01 08:34:08 +02:00
riscv softfloat: Implement the full set of comparisons for float16 2020-08-28 10:48:07 -07:00
rx rx: Move typedef RXCPU to cpu-qom.h 2020-09-02 07:29:25 -04:00
s390x target/s390x: fix meson.build issue 2020-08-21 11:55:13 -04:00
sh4 target/sh4: Remove superfluous breaks 2020-09-01 08:38:41 +02:00
sparc meson: target 2020-08-21 06:30:35 -04:00
tilegx meson: target 2020-08-21 06:30:35 -04:00
tricore meson: target 2020-08-21 06:30:35 -04:00
unicore32 meson: target 2020-08-21 06:30:35 -04:00
xtensa target/xtensa: import DSP3400 core 2020-08-21 12:56:45 -07:00
meson.build meson: target 2020-08-21 06:30:35 -04:00