qemu/target
Philipp Tomsich 54c1760937 target/riscv: Fix orc.b implementation
The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).

This changes the algorithm to:
 1. Mask out the high-bit of each bytes (so that each byte is <= 127).
 2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
    into the highest bit of each byte).
 3. Bitwise-or the original value back in (to cover those cases where the
    source byte was exactly 128) to saturate the high-bit.
 4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
    each byte into its LSB.
 5. Multiply with 0xff to fan out the LSB to all bits of each byte.

Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci")

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reported-by: Vincent Palatin <vpalatin@rivosinc.com>
Tested-by: Vincent Palatin <vpalatin@rivosinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22 07:47:51 +10:00
..
alpha target/alpha: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
arm target/arm: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
avr target/avr: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
cris target/cris: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
hexagon target/hexagon: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
hppa target/hppa: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
i386 target/i386: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
m68k target/m68k: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
microblaze target/microblaze: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
mips target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn() 2021-10-18 00:41:36 +02:00
nios2 hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
openrisc target/openrisc: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
ppc target/ppc: adding user read/write functions for PMCs 2021-10-21 11:42:47 +11:00
riscv target/riscv: Fix orc.b implementation 2021-10-22 07:47:51 +10:00
rx target/rx: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
s390x target/s390x: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
sh4 target/sh4: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
sparc target/sparc: Use cpu_*_mmu instead of helper_*_mmu 2021-10-13 08:45:13 -07:00
tricore target/tricore: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
xtensa target/xtensa: Drop check for singlestep_enabled 2021-10-15 16:39:15 -07:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00