Daniel Henrique Barboza 54bd9b6ec3 target/riscv: allow MISA writes as experimental ... At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because write_misa() will always exit earlier. This seems to be benign in the majority of cases. Booting an Ubuntu 'virt' guest and logging all the calls to 'write_misa' shows that no writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling RISC-V extensions after the machine is powered on, seems to be a niche use. After discussions in the mailing list, most notably in [1], we reached the consensus that this code is not suited to be exposed to users because it's not well tested, but at the same time removing it is a bit extreme because we would like to fix it, and it's easier to do so with the code available to use instead of fetching it from git log. The approach taken here is to get rid of RISCV_FEATURE_MISA altogether and use a new experimental flag called x-misa-w. The default value is false, meaning that we're keeping the existing behavior of doing nothing if a write_misa() is attempted. As with any existing experimental flag, x-misa-w is also a temporary flag that we need to remove once we fix write_misa(). [1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05092.html Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-03-01 13:47:10 -08:00
..
alpha	target/alpha: Remove obsolete STATUS document	2023-02-27 22:29:01 +01:00
arm	target/cpu: Restrict do_transaction_failed() handlers to sysemu	2023-02-27 22:29:01 +01:00
avr	target/avr: Convert to 3-phase reset	2022-12-16 15:58:15 +00:00
cris	target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu	2023-02-27 22:29:01 +01:00
hexagon	target/hexagon: Clean up includes	2023-02-08 07:28:05 +01:00
hppa	target/hppa: Extract system helpers to sys_helper.c	2023-02-27 22:29:01 +01:00
i386	- buildsys	2023-02-28 15:09:18 +00:00
loongarch	target/loongarch/cpu: Restrict "memory.h" header to sysemu	2023-02-27 22:29:01 +01:00
m68k	target/cpu: Restrict do_transaction_failed() handlers to sysemu	2023-02-27 22:29:01 +01:00
microblaze	target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu	2023-02-27 22:29:01 +01:00
mips	Drop duplicate #include	2023-02-08 07:28:05 +01:00
nios2	target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu	2023-02-27 22:29:01 +01:00
openrisc	target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu	2023-02-27 22:29:01 +01:00
ppc	target/ppc: Fix warning with clang-15	2023-02-27 22:29:01 +01:00
riscv	target/riscv: allow MISA writes as experimental	2023-03-01 13:47:10 -08:00
rx	target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu	2023-02-27 22:29:01 +01:00
s390x	target/s390x: Use tcg_constant_* in translate_vx.c.inc	2023-02-27 09:15:39 +01:00
sh4	target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu	2023-02-27 22:29:01 +01:00
sparc	target/sparc/sysemu: Remove pointless CONFIG_USER_ONLY guard	2023-02-27 22:29:01 +01:00
tricore	target/tricore: Remove unused fields from CPUTriCoreState	2023-02-27 22:29:01 +01:00
xtensa	target/xtensa/cpu: Include missing "memory.h" header	2023-02-27 22:29:01 +01:00
Kconfig	hw/loongarch: Add support loongson3 virt machine type.	2022-06-06 18:09:03 +00:00
meson.build	target/loongarch: Add target build suport	2022-06-06 18:09:03 +00:00