2e2ca3c8fa
1.helper_asrtle_d/helper_asrtgt_d need use GETPC() to get PC;
2 LD/ST{LE/GT} need set CSR_BADV = gpr[rj];
3 ASRTLE.D/ASRTGT.D also write CSR_BADV, but this value is random
and has no reference value.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230515130042.2719712-1-gaosong@loongson.cn>
142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch emulation helpers for QEMU.
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "internals.h"
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#include "qemu/crc32c.h"
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#include <zlib.h>
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#include "cpu-csr.h"
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/* Exceptions helpers */
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void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
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{
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do_raise_exception(env, exception, GETPC());
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}
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target_ulong helper_bitrev_w(target_ulong rj)
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{
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return (int32_t)revbit32(rj);
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}
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target_ulong helper_bitrev_d(target_ulong rj)
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{
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return revbit64(rj);
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}
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target_ulong helper_bitswap(target_ulong v)
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{
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v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
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((v & (target_ulong)0x5555555555555555ULL) << 1);
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v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
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((v & (target_ulong)0x3333333333333333ULL) << 2);
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v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
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((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
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return v;
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}
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/* loongarch assert op */
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void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
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{
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if (rj > rk) {
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env->CSR_BADV = rj;
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do_raise_exception(env, EXCCODE_BCE, GETPC());
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}
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}
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void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
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{
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if (rj <= rk) {
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env->CSR_BADV = rj;
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do_raise_exception(env, EXCCODE_BCE, GETPC());
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}
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}
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target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
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{
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uint8_t buf[8];
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target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
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m &= mask;
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stq_le_p(buf, m);
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return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
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}
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target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
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{
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uint8_t buf[8];
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target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
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m &= mask;
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stq_le_p(buf, m);
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return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff);
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}
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target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
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{
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return rj >= ARRAY_SIZE(env->cpucfg) ? 0 : env->cpucfg[rj];
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}
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uint64_t helper_rdtime_d(CPULoongArchState *env)
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{
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#ifdef CONFIG_USER_ONLY
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return cpu_get_host_ticks();
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#else
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uint64_t plv;
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LoongArchCPU *cpu = env_archcpu(env);
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plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
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if (extract64(env->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) {
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do_raise_exception(env, EXCCODE_IPE, GETPC());
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}
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return cpu_loongarch_get_constant_timer_counter(cpu);
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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void helper_ertn(CPULoongArchState *env)
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{
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uint64_t csr_pplv, csr_pie;
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if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
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csr_pplv = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV);
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csr_pie = FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE);
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env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1);
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env->pc = env->CSR_TLBRERA;
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qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n",
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__func__, env->CSR_TLBRERA);
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} else {
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csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV);
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csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE);
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env->pc = env->CSR_ERA;
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qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n",
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__func__, env->CSR_ERA);
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}
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, csr_pplv);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, csr_pie);
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env->lladdr = 1;
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}
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void helper_idle(CPULoongArchState *env)
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{
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CPUState *cs = env_cpu(env);
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cs->halted = 1;
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do_raise_exception(env, EXCP_HLT, 0);
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}
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#endif
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