Jim Wilson 5371f5cd71 RISC-V: Add hooks to use the gdb xml files. ... The gdb CSR xml file has registers in documentation order, not numerical order, so we need a table to map the register numbers. This also adds fairly standard gdb hooks to access xml specified registers. notice: The fpu xml from gdb 8.3 has unused register #, 65 and make first csr register # become 69. We register extra register on gdb to correct csr offset calculation Signed-off-by: Jim Wilson <jimw@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-03-19 05:13:24 -07:00
..
insn_trans	target/riscv: Fix manually parsed 16 bit insn	2019-03-17 22:21:32 -07:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 05:13:24 -07:00
cpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Add hooks to use the gdb xml files.	2019-03-19 05:13:24 -07:00
cpu.h	RISC-V: Add hooks to use the gdb xml files.	2019-03-19 05:13:24 -07:00
csr.c	RISC-V: Add debug support for accessing CSRs.	2019-03-19 05:13:24 -07:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	RISC-V: Add hooks to use the gdb xml files.	2019-03-19 05:13:24 -07:00
helper.h
insn16.decode	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-13 10:40:46 +01:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-13 10:34:06 +01:00
insn32.decode	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-13 10:40:50 +01:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-13 10:34:06 +01:00
op_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
pmp.c	target/riscv/pmp.c: Fix pmp_decode_napot()	2018-12-20 12:26:39 -08:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target/riscv: Remove decode_RV32_64G()	2019-03-13 10:40:50 +01:00