5325cc34a2
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
429 lines
14 KiB
C
429 lines
14 KiB
C
/*
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* QEMU MIPS Jazz support
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*
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* Copyright (c) 2007-2008 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/cpudevs.h"
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#include "hw/intc/i8259.h"
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#include "hw/dma/i8257.h"
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#include "hw/char/serial.h"
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#include "hw/char/parallel.h"
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#include "hw/isa/isa.h"
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#include "hw/block/fdc.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/arch_init.h"
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#include "hw/boards.h"
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#include "net/net.h"
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#include "hw/scsi/esp.h"
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#include "hw/mips/bios.h"
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#include "hw/loader.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/timer/i8254.h"
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#include "hw/display/vga.h"
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#include "hw/audio/pcspk.h"
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#include "hw/input/i8042.h"
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#include "hw/sysbus.h"
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#include "exec/address-spaces.h"
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#include "sysemu/qtest.h"
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#include "sysemu/reset.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/help_option.h"
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enum jazz_model_e {
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JAZZ_MAGNUM,
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JAZZ_PICA61,
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};
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static void main_cpu_reset(void *opaque)
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{
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MIPSCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
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{
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uint8_t val;
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address_space_read(&address_space_memory, 0x90000071,
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MEMTXATTRS_UNSPECIFIED, &val, 1);
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return val;
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}
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static void rtc_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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uint8_t buf = val & 0xff;
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address_space_write(&address_space_memory, 0x90000071,
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MEMTXATTRS_UNSPECIFIED, &buf, 1);
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}
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static const MemoryRegionOps rtc_ops = {
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.read = rtc_read,
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.write = rtc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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/*
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* Nothing to do. That is only to ensure that
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* the current DMA acknowledge cycle is completed.
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*/
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return 0xff;
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}
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static void dma_dummy_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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/*
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* Nothing to do. That is only to ensure that
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* the current DMA acknowledge cycle is completed.
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*/
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}
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static const MemoryRegionOps dma_dummy_ops = {
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.read = dma_dummy_read,
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.write = dma_dummy_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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#define MAGNUM_BIOS_SIZE_MAX 0x7e000
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#define MAGNUM_BIOS_SIZE \
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(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
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static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response,
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uintptr_t retaddr);
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static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response,
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uintptr_t retaddr)
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{
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if (access_type != MMU_INST_FETCH) {
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/* ignore invalid access (ie do not raise exception) */
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return;
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}
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(*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
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mmu_idx, attrs, response, retaddr);
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}
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static void mips_jazz_init(MachineState *machine,
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enum jazz_model_e jazz_model)
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{
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MemoryRegion *address_space = get_system_memory();
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char *filename;
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int bios_size, n;
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MIPSCPU *cpu;
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CPUClass *cc;
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CPUMIPSState *env;
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qemu_irq *i8259;
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rc4030_dma *dmas;
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IOMMUMemoryRegion *rc4030_dma_mr;
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MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
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MemoryRegion *isa_io = g_new(MemoryRegion, 1);
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MemoryRegion *rtc = g_new(MemoryRegion, 1);
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MemoryRegion *i8042 = g_new(MemoryRegion, 1);
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MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
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NICInfo *nd;
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DeviceState *dev, *rc4030;
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SysBusDevice *sysbus;
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ISABus *isa_bus;
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ISADevice *pit;
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DriveInfo *fds[MAX_FD];
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MemoryRegion *bios = g_new(MemoryRegion, 1);
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MemoryRegion *bios2 = g_new(MemoryRegion, 1);
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SysBusESPState *sysbus_esp;
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ESPState *esp;
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if (machine->ram_size > 256 * MiB) {
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error_report("RAM size more than 256Mb is not supported");
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exit(EXIT_FAILURE);
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}
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/* init CPUs */
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cpu = MIPS_CPU(cpu_create(machine->cpu_type));
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env = &cpu->env;
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qemu_register_reset(main_cpu_reset, cpu);
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/*
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* Chipset returns 0 in invalid reads and do not raise data exceptions.
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* However, we can't simply add a global memory region to catch
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* everything, as this would make all accesses including instruction
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* accesses be ignored and not raise exceptions.
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* So instead we hijack the do_transaction_failed method on the CPU, and
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* do not raise exceptions for data access.
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*
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* NOTE: this behaviour of raising exceptions for bad instruction
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* fetches but not bad data accesses was added in commit 54e755588cf1e9
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* to restore behaviour broken by c658b94f6e8c206, but it is not clear
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* whether the real hardware behaves this way. It is possible that
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* real hardware ignores bad instruction fetches as well -- if so then
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* we could replace this hijacking of CPU methods with a simple global
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* memory region that catches all memory accesses, as we do on Malta.
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*/
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cc = CPU_GET_CLASS(cpu);
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real_do_transaction_failed = cc->do_transaction_failed;
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cc->do_transaction_failed = mips_jazz_do_transaction_failed;
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/* allocate RAM */
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memory_region_add_subregion(address_space, 0, machine->ram);
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memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
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&error_fatal);
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memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
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0, MAGNUM_BIOS_SIZE);
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memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
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memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
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/* load the BIOS image. */
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if (bios_name == NULL) {
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bios_name = BIOS_FILENAME;
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}
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (filename) {
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bios_size = load_image_targphys(filename, 0xfff00000LL,
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MAGNUM_BIOS_SIZE);
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g_free(filename);
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} else {
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bios_size = -1;
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}
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if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
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error_report("Could not load MIPS bios '%s'", bios_name);
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exit(1);
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}
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/* Init CPU internal devices */
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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/* Chipset */
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rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
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sysbus = SYS_BUS_DEVICE(rc4030);
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sysbus_connect_irq(sysbus, 0, env->irq[6]);
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sysbus_connect_irq(sysbus, 1, env->irq[3]);
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memory_region_add_subregion(address_space, 0x80000000,
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sysbus_mmio_get_region(sysbus, 0));
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memory_region_add_subregion(address_space, 0xf0000000,
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sysbus_mmio_get_region(sysbus, 1));
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memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops,
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NULL, "dummy_dma", 0x1000);
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memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
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/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
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memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
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memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
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memory_region_add_subregion(address_space, 0x90000000, isa_io);
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memory_region_add_subregion(address_space, 0x91000000, isa_mem);
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isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
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/* ISA devices */
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i8259 = i8259_init(isa_bus, env->irq[4]);
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isa_bus_irqs(isa_bus, i8259);
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i8257_dma_init(isa_bus, 0);
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pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
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pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit);
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/* Video card */
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switch (jazz_model) {
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case JAZZ_MAGNUM:
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dev = qdev_new("sysbus-g364");
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sysbus = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 0, 0x60080000);
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sysbus_mmio_map(sysbus, 1, 0x40000000);
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sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
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{
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/* Simple ROM, so user doesn't have to provide one */
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MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
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memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000,
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&error_fatal);
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uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
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memory_region_add_subregion(address_space, 0x60000000, rom_mr);
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rom[0] = 0x10; /* Mips G364 */
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}
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break;
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case JAZZ_PICA61:
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isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
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break;
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default:
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break;
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}
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/* Network controller */
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for (n = 0; n < nb_nics; n++) {
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nd = &nd_table[n];
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if (!nd->model) {
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nd->model = g_strdup("dp83932");
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}
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if (strcmp(nd->model, "dp83932") == 0) {
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qemu_check_nic_model(nd, "dp83932");
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dev = qdev_new("dp8393x");
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qdev_set_nic_properties(dev, nd);
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qdev_prop_set_uint8(dev, "it_shift", 2);
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object_property_set_link(OBJECT(dev), "dma_mr",
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OBJECT(rc4030_dma_mr), &error_abort);
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sysbus = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 0, 0x80001000);
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sysbus_mmio_map(sysbus, 1, 0x8000b000);
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sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
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break;
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} else if (is_help_option(nd->model)) {
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error_report("Supported NICs: dp83932");
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exit(1);
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} else {
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error_report("Unsupported NIC: %s", nd->model);
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exit(1);
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}
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}
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/* SCSI adapter */
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dev = qdev_new(TYPE_ESP);
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sysbus_esp = ESP_STATE(dev);
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esp = &sysbus_esp->esp;
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esp->dma_memory_read = rc4030_dma_read;
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esp->dma_memory_write = rc4030_dma_write;
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esp->dma_opaque = dmas[0];
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sysbus_esp->it_shift = 0;
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/* XXX for now until rc4030 has been changed to use DMA enable signal */
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esp->dma_enabled = 1;
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sysbus = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
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sysbus_mmio_map(sysbus, 0, 0x80002000);
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scsi_bus_legacy_handle_cmdline(&esp->bus);
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/* Floppy */
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for (n = 0; n < MAX_FD; n++) {
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fds[n] = drive_get(IF_FLOPPY, 0, n);
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}
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/* FIXME: we should enable DMA with a custom IsaDma device */
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fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
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/* Real time clock */
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mc146818_rtc_init(isa_bus, 1980, NULL);
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memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
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memory_region_add_subregion(address_space, 0x80004000, rtc);
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/* Keyboard (i8042) */
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i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
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i8042, 0x1000, 0x1);
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memory_region_add_subregion(address_space, 0x80005000, i8042);
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/* Serial ports */
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if (serial_hd(0)) {
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serial_mm_init(address_space, 0x80006000, 0,
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qdev_get_gpio_in(rc4030, 8), 8000000 / 16,
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serial_hd(0), DEVICE_NATIVE_ENDIAN);
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}
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if (serial_hd(1)) {
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serial_mm_init(address_space, 0x80007000, 0,
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qdev_get_gpio_in(rc4030, 9), 8000000 / 16,
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serial_hd(1), DEVICE_NATIVE_ENDIAN);
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}
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/* Parallel port */
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if (parallel_hds[0])
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parallel_mm_init(address_space, 0x80008000, 0,
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qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
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/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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/* NVRAM */
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dev = qdev_new("ds1225y");
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sysbus = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 0, 0x80009000);
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/* LED indicator */
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sysbus_create_simple("jazz-led", 0x8000f000, NULL);
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g_free(dmas);
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}
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static
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void mips_magnum_init(MachineState *machine)
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{
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mips_jazz_init(machine, JAZZ_MAGNUM);
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}
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static
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void mips_pica61_init(MachineState *machine)
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{
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mips_jazz_init(machine, JAZZ_PICA61);
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}
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static void mips_magnum_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "MIPS Magnum";
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mc->init = mips_magnum_init;
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mc->block_default_type = IF_SCSI;
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mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
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mc->default_ram_id = "mips_jazz.ram";
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}
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static const TypeInfo mips_magnum_type = {
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.name = MACHINE_TYPE_NAME("magnum"),
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.parent = TYPE_MACHINE,
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.class_init = mips_magnum_class_init,
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};
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static void mips_pica61_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "Acer Pica 61";
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mc->init = mips_pica61_init;
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mc->block_default_type = IF_SCSI;
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mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
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mc->default_ram_id = "mips_jazz.ram";
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}
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static const TypeInfo mips_pica61_type = {
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.name = MACHINE_TYPE_NAME("pica61"),
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.parent = TYPE_MACHINE,
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.class_init = mips_pica61_class_init,
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};
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static void mips_jazz_machine_init(void)
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{
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type_register_static(&mips_magnum_type);
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type_register_static(&mips_pica61_type);
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}
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type_init(mips_jazz_machine_init)
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