52fc1d83bc
Note that other PCI bridges are not fixed here. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3793 c046a42c-6fe2-441c-8c8c-71466251a162
698 lines
20 KiB
C
698 lines
20 KiB
C
/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "console.h"
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#include "net.h"
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//#define DEBUG_PCI
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struct PCIBus {
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int bus_num;
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int devfn_min;
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pci_set_irq_fn set_irq;
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pci_map_irq_fn map_irq;
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uint32_t config_reg; /* XXX: suppress */
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/* low level pic */
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SetIRQFunc *low_set_irq;
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qemu_irq *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *parent_dev;
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PCIBus *next;
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int irq_count[];
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};
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static void pci_update_mappings(PCIDevice *d);
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static void pci_set_irq(void *opaque, int irq_num, int level);
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target_phys_addr_t pci_mem_base;
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static int pci_irq_index;
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static PCIBus *first_bus;
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static void pcibus_save(QEMUFile *f, void *opaque)
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{
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PCIBus *bus = (PCIBus *)opaque;
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int i;
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qemu_put_be32(f, bus->nirq);
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for (i = 0; i < bus->nirq; i++)
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qemu_put_be32(f, bus->irq_count[i]);
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}
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static int pcibus_load(QEMUFile *f, void *opaque, int version_id)
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{
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PCIBus *bus = (PCIBus *)opaque;
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int i, nirq;
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if (version_id != 1)
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return -EINVAL;
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nirq = qemu_get_be32(f);
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if (bus->nirq != nirq) {
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fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
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nirq, bus->nirq);
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return -EINVAL;
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}
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for (i = 0; i < nirq; i++)
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bus->irq_count[i] = qemu_get_be32(f);
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return 0;
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}
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PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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qemu_irq *pic, int devfn_min, int nirq)
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{
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PCIBus *bus;
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static int nbus = 0;
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bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
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bus->set_irq = set_irq;
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bus->map_irq = map_irq;
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bus->irq_opaque = pic;
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bus->devfn_min = devfn_min;
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bus->nirq = nirq;
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first_bus = bus;
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register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
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return bus;
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}
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static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
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{
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PCIBus *bus;
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bus = qemu_mallocz(sizeof(PCIBus));
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bus->map_irq = map_irq;
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bus->parent_dev = dev;
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bus->next = dev->bus->next;
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dev->bus->next = bus;
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return bus;
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}
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int pci_bus_num(PCIBus *s)
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{
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return s->bus_num;
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}
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void pci_device_save(PCIDevice *s, QEMUFile *f)
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{
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int i;
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qemu_put_be32(f, 2); /* PCI device version */
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qemu_put_buffer(f, s->config, 256);
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for (i = 0; i < 4; i++)
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qemu_put_be32(f, s->irq_state[i]);
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}
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int pci_device_load(PCIDevice *s, QEMUFile *f)
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{
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uint32_t version_id;
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int i;
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version_id = qemu_get_be32(f);
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if (version_id > 2)
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return -EINVAL;
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qemu_get_buffer(f, s->config, 256);
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pci_update_mappings(s);
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if (version_id >= 2)
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for (i = 0; i < 4; i ++)
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s->irq_state[i] = qemu_get_be32(f);
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return 0;
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}
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/* -1 for devfn means auto assign */
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PCIDevice *pci_register_device(PCIBus *bus, const char *name,
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int instance_size, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write)
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{
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PCIDevice *pci_dev;
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if (pci_irq_index >= PCI_DEVICES_MAX)
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return NULL;
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if (devfn < 0) {
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for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
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if (!bus->devices[devfn])
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goto found;
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}
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return NULL;
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found: ;
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}
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pci_dev = qemu_mallocz(instance_size);
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if (!pci_dev)
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return NULL;
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pci_dev->bus = bus;
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pci_dev->devfn = devfn;
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pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
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if (!config_read)
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config_read = pci_default_read_config;
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if (!config_write)
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config_write = pci_default_write_config;
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pci_dev->config_read = config_read;
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pci_dev->config_write = config_write;
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pci_dev->irq_index = pci_irq_index++;
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bus->devices[devfn] = pci_dev;
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pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
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return pci_dev;
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}
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void pci_register_io_region(PCIDevice *pci_dev, int region_num,
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func)
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{
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PCIIORegion *r;
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uint32_t addr;
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if ((unsigned int)region_num >= PCI_NUM_REGIONS)
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return;
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r = &pci_dev->io_regions[region_num];
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r->addr = -1;
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r->size = size;
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r->type = type;
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r->map_func = map_func;
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if (region_num == PCI_ROM_SLOT) {
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addr = 0x30;
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} else {
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addr = 0x10 + region_num * 4;
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}
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*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
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}
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static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
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{
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return addr + pci_mem_base;
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}
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static void pci_update_mappings(PCIDevice *d)
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{
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PCIIORegion *r;
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int cmd, i;
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uint32_t last_addr, new_addr, config_ofs;
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cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
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for(i = 0; i < PCI_NUM_REGIONS; i++) {
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r = &d->io_regions[i];
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if (i == PCI_ROM_SLOT) {
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config_ofs = 0x30;
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} else {
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config_ofs = 0x10 + i * 4;
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}
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if (r->size != 0) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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config_ofs));
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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if (last_addr <= new_addr || new_addr == 0 ||
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last_addr >= 0x10000) {
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new_addr = -1;
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}
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} else {
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new_addr = -1;
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}
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} else {
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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config_ofs));
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/* the ROM slot has a specific enable bit */
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if (i == PCI_ROM_SLOT && !(new_addr & 1))
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goto no_mem_map;
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we do not support wrapping */
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/* XXX: as we cannot support really dynamic
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mappings, we handle specific values as invalid
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mappings. */
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if (last_addr <= new_addr || new_addr == 0 ||
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last_addr == -1) {
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new_addr = -1;
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}
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} else {
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no_mem_map:
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new_addr = -1;
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}
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}
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/* now do the real mapping */
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if (new_addr != r->addr) {
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if (r->addr != -1) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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int class;
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/* NOTE: specific hack for IDE in PC case:
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only one byte must be mapped. */
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class = d->config[0x0a] | (d->config[0x0b] << 8);
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if (class == 0x0101 && r->size == 4) {
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isa_unassign_ioport(r->addr + 2, 1);
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} else {
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isa_unassign_ioport(r->addr, r->size);
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}
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} else {
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cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
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r->size,
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IO_MEM_UNASSIGNED);
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}
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}
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r->addr = new_addr;
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if (r->addr != -1) {
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r->map_func(d, i, r->addr, r->size, r->type);
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}
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}
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}
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}
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}
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uint32_t pci_default_read_config(PCIDevice *d,
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uint32_t address, int len)
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{
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uint32_t val;
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switch(len) {
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default:
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case 4:
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if (address <= 0xfc) {
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val = le32_to_cpu(*(uint32_t *)(d->config + address));
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break;
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}
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/* fall through */
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case 2:
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if (address <= 0xfe) {
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val = le16_to_cpu(*(uint16_t *)(d->config + address));
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break;
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}
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/* fall through */
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case 1:
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val = d->config[address];
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break;
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}
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return val;
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}
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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int can_write, i;
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uint32_t end, addr;
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if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
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(address >= 0x30 && address < 0x34))) {
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PCIIORegion *r;
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int reg;
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if ( address >= 0x30 ) {
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reg = PCI_ROM_SLOT;
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}else{
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reg = (address - 0x10) >> 2;
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}
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r = &d->io_regions[reg];
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if (r->size == 0)
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goto default_config;
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/* compute the stored value */
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if (reg == PCI_ROM_SLOT) {
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/* keep ROM enable bit */
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val &= (~(r->size - 1)) | 1;
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} else {
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val &= ~(r->size - 1);
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val |= r->type;
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}
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*(uint32_t *)(d->config + address) = cpu_to_le32(val);
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pci_update_mappings(d);
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return;
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}
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default_config:
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/* not efficient, but simple */
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addr = address;
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for(i = 0; i < len; i++) {
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/* default read/write accesses */
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switch(d->config[0x0e]) {
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case 0x00:
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case 0x80:
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switch(addr) {
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0e:
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case 0x10 ... 0x27: /* base */
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case 0x30 ... 0x33: /* rom */
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case 0x3d:
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can_write = 0;
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break;
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default:
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can_write = 1;
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break;
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}
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break;
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default:
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case 0x01:
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switch(addr) {
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x03:
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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case 0x0e:
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case 0x38 ... 0x3b: /* rom */
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case 0x3d:
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can_write = 0;
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break;
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default:
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can_write = 1;
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break;
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}
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break;
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}
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if (can_write) {
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d->config[addr] = val;
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}
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if (++addr > 0xff)
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break;
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val >>= 8;
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}
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end = address + len;
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if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
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/* if the command register is modified, we must modify the mappings */
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pci_update_mappings(d);
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}
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}
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void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
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{
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PCIBus *s = opaque;
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PCIDevice *pci_dev;
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int config_addr, bus_num;
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#if defined(DEBUG_PCI) && 0
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printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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addr, val, len);
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#endif
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bus_num = (addr >> 16) & 0xff;
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while (s && s->bus_num != bus_num)
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s = s->next;
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if (!s)
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return;
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pci_dev = s->devices[(addr >> 8) & 0xff];
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if (!pci_dev)
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return;
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config_addr = addr & 0xff;
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#if defined(DEBUG_PCI)
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printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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pci_dev->name, config_addr, val, len);
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#endif
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pci_dev->config_write(pci_dev, config_addr, val, len);
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}
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uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
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{
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PCIBus *s = opaque;
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PCIDevice *pci_dev;
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int config_addr, bus_num;
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uint32_t val;
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bus_num = (addr >> 16) & 0xff;
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while (s && s->bus_num != bus_num)
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s= s->next;
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if (!s)
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goto fail;
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pci_dev = s->devices[(addr >> 8) & 0xff];
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if (!pci_dev) {
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fail:
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switch(len) {
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case 1:
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val = 0xff;
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break;
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case 2:
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val = 0xffff;
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break;
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default:
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case 4:
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val = 0xffffffff;
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break;
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}
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goto the_end;
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}
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config_addr = addr & 0xff;
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val = pci_dev->config_read(pci_dev, config_addr, len);
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#if defined(DEBUG_PCI)
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printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
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pci_dev->name, config_addr, val, len);
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#endif
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the_end:
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#if defined(DEBUG_PCI) && 0
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printf("pci_data_read: addr=%08x val=%08x len=%d\n",
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addr, val, len);
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#endif
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return val;
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}
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/***********************************************************/
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/* generic PCI irq support */
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/* 0 <= irq_num <= 3. level must be 0 or 1 */
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static void pci_set_irq(void *opaque, int irq_num, int level)
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{
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PCIDevice *pci_dev = (PCIDevice *)opaque;
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PCIBus *bus;
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int change;
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change = level - pci_dev->irq_state[irq_num];
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if (!change)
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return;
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pci_dev->irq_state[irq_num] = level;
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for (;;) {
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bus = pci_dev->bus;
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irq_num = bus->map_irq(pci_dev, irq_num);
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if (bus->set_irq)
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break;
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pci_dev = bus->parent_dev;
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}
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bus->irq_count[irq_num] += change;
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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}
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/***********************************************************/
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/* monitor info on PCI */
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typedef struct {
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uint16_t class;
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const char *desc;
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} pci_class_desc;
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static pci_class_desc pci_class_descriptions[] =
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{
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|
{ 0x0100, "SCSI controller"},
|
|
{ 0x0101, "IDE controller"},
|
|
{ 0x0102, "Floppy controller"},
|
|
{ 0x0103, "IPI controller"},
|
|
{ 0x0104, "RAID controller"},
|
|
{ 0x0106, "SATA controller"},
|
|
{ 0x0107, "SAS controller"},
|
|
{ 0x0180, "Storage controller"},
|
|
{ 0x0200, "Ethernet controller"},
|
|
{ 0x0201, "Token Ring controller"},
|
|
{ 0x0202, "FDDI controller"},
|
|
{ 0x0203, "ATM controller"},
|
|
{ 0x0280, "Network controller"},
|
|
{ 0x0300, "VGA controller"},
|
|
{ 0x0301, "XGA controller"},
|
|
{ 0x0302, "3D controller"},
|
|
{ 0x0380, "Display controller"},
|
|
{ 0x0400, "Video controller"},
|
|
{ 0x0401, "Audio controller"},
|
|
{ 0x0402, "Phone"},
|
|
{ 0x0480, "Multimedia controller"},
|
|
{ 0x0500, "RAM controller"},
|
|
{ 0x0501, "Flash controller"},
|
|
{ 0x0580, "Memory controller"},
|
|
{ 0x0600, "Host bridge"},
|
|
{ 0x0601, "ISA bridge"},
|
|
{ 0x0602, "EISA bridge"},
|
|
{ 0x0603, "MC bridge"},
|
|
{ 0x0604, "PCI bridge"},
|
|
{ 0x0605, "PCMCIA bridge"},
|
|
{ 0x0606, "NUBUS bridge"},
|
|
{ 0x0607, "CARDBUS bridge"},
|
|
{ 0x0608, "RACEWAY bridge"},
|
|
{ 0x0680, "Bridge"},
|
|
{ 0x0c03, "USB controller"},
|
|
{ 0, NULL}
|
|
};
|
|
|
|
static void pci_info_device(PCIDevice *d)
|
|
{
|
|
int i, class;
|
|
PCIIORegion *r;
|
|
pci_class_desc *desc;
|
|
|
|
term_printf(" Bus %2d, device %3d, function %d:\n",
|
|
d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
|
|
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
|
|
term_printf(" ");
|
|
desc = pci_class_descriptions;
|
|
while (desc->desc && class != desc->class)
|
|
desc++;
|
|
if (desc->desc) {
|
|
term_printf("%s", desc->desc);
|
|
} else {
|
|
term_printf("Class %04x", class);
|
|
}
|
|
term_printf(": PCI device %04x:%04x\n",
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
|
|
|
|
if (d->config[PCI_INTERRUPT_PIN] != 0) {
|
|
term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
|
}
|
|
if (class == 0x0604) {
|
|
term_printf(" BUS %d.\n", d->config[0x19]);
|
|
}
|
|
for(i = 0;i < PCI_NUM_REGIONS; i++) {
|
|
r = &d->io_regions[i];
|
|
if (r->size != 0) {
|
|
term_printf(" BAR%d: ", i);
|
|
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
|
term_printf("I/O at 0x%04x [0x%04x].\n",
|
|
r->addr, r->addr + r->size - 1);
|
|
} else {
|
|
term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
|
r->addr, r->addr + r->size - 1);
|
|
}
|
|
}
|
|
}
|
|
if (class == 0x0604 && d->config[0x19] != 0) {
|
|
pci_for_each_device(d->config[0x19], pci_info_device);
|
|
}
|
|
}
|
|
|
|
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
|
|
{
|
|
PCIBus *bus = first_bus;
|
|
PCIDevice *d;
|
|
int devfn;
|
|
|
|
while (bus && bus->bus_num != bus_num)
|
|
bus = bus->next;
|
|
if (bus) {
|
|
for(devfn = 0; devfn < 256; devfn++) {
|
|
d = bus->devices[devfn];
|
|
if (d)
|
|
fn(d);
|
|
}
|
|
}
|
|
}
|
|
|
|
void pci_info(void)
|
|
{
|
|
pci_for_each_device(0, pci_info_device);
|
|
}
|
|
|
|
/* Initialize a PCI NIC. */
|
|
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn)
|
|
{
|
|
if (strcmp(nd->model, "ne2k_pci") == 0) {
|
|
pci_ne2000_init(bus, nd, devfn);
|
|
} else if (strcmp(nd->model, "i82551") == 0) {
|
|
pci_i82551_init(bus, nd, devfn);
|
|
} else if (strcmp(nd->model, "i82557b") == 0) {
|
|
pci_i82557b_init(bus, nd, devfn);
|
|
} else if (strcmp(nd->model, "i82559er") == 0) {
|
|
pci_i82559er_init(bus, nd, devfn);
|
|
} else if (strcmp(nd->model, "rtl8139") == 0) {
|
|
pci_rtl8139_init(bus, nd, devfn);
|
|
} else if (strcmp(nd->model, "pcnet") == 0) {
|
|
pci_pcnet_init(bus, nd, devfn);
|
|
} else if (strcmp(nd->model, "?") == 0) {
|
|
fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
|
|
" ne2k_pci pcnet rtl8139\n");
|
|
exit (1);
|
|
} else {
|
|
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
|
|
exit (1);
|
|
}
|
|
}
|
|
|
|
typedef struct {
|
|
PCIDevice dev;
|
|
PCIBus *bus;
|
|
} PCIBridge;
|
|
|
|
static void pci_bridge_write_config(PCIDevice *d,
|
|
uint32_t address, uint32_t val, int len)
|
|
{
|
|
PCIBridge *s = (PCIBridge *)d;
|
|
|
|
if (address == 0x19 || (address == 0x18 && len > 1)) {
|
|
if (address == 0x19)
|
|
s->bus->bus_num = val & 0xff;
|
|
else
|
|
s->bus->bus_num = (val >> 8) & 0xff;
|
|
#if defined(DEBUG_PCI)
|
|
printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
|
|
#endif
|
|
}
|
|
pci_default_write_config(d, address, val, len);
|
|
}
|
|
|
|
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
|
pci_map_irq_fn map_irq, const char *name)
|
|
{
|
|
PCIBridge *s;
|
|
s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
|
|
devfn, NULL, pci_bridge_write_config);
|
|
s->dev.config[0x00] = id >> 16;
|
|
s->dev.config[0x01] = id >> 24;
|
|
s->dev.config[0x02] = id; // device_id
|
|
s->dev.config[0x03] = id >> 8;
|
|
s->dev.config[0x04] = 0x06; // command = bus master, pci mem
|
|
s->dev.config[0x05] = 0x00;
|
|
s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
|
|
s->dev.config[0x07] = 0x00; // status = fast devsel
|
|
s->dev.config[0x08] = 0x00; // revision
|
|
s->dev.config[0x09] = 0x00; // programming i/f
|
|
s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
|
|
s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
|
|
s->dev.config[0x0D] = 0x10; // latency_timer
|
|
s->dev.config[0x0E] = 0x81; // header_type
|
|
s->dev.config[0x1E] = 0xa0; // secondary status
|
|
|
|
s->bus = pci_register_secondary_bus(&s->dev, map_irq);
|
|
return s->bus;
|
|
}
|