478d360cd9
Suppose psw.mask=0x0000000080000000, cc=2, r1=0 and we do "ipm 1". This command must touch only bits 32-39, so the expected output is r1=0x20000000. However, currently qemu yields r1=0x20008000, because irrelevant parts of PSW leak into r1 during program mask transfer. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-5-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
23 lines
457 B
C
23 lines
457 B
C
#include <stdint.h>
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#include <unistd.h>
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int main(void)
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{
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uint32_t op1 = 0x55555555;
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uint32_t op2 = 0x44444444;
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uint64_t cc = 0xffffffffffffffffull;
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asm volatile(
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" clc 0(4,%[op1]),0(%[op2])\n"
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" ipm %[cc]\n"
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: [cc] "+r" (cc)
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: [op1] "r" (&op1),
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[op2] "r" (&op2)
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: "cc");
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if (cc != 0xffffffff20ffffffull) {
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write(1, "bad cc\n", 7);
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return 1;
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}
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return 0;
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}
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