Richard Henderson ec2918b467 target/riscv: Set pc_succ_insn for !rvc illegal insn ... Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-06 10:42:55 +10:00
..
issue1060.S	target/riscv: Set env->bins in gen_exception_illegal	2022-07-03 10:03:20 +10:00
Makefile.softmmu-target	target/riscv: Set env->bins in gen_exception_illegal	2022-07-03 10:03:20 +10:00
Makefile.target	target/riscv: Set pc_succ_insn for !rvc illegal insn	2023-01-06 10:42:55 +10:00
noexec.c	target/riscv: Make translator stop before the end of a page	2022-09-06 08:04:26 +01:00
semicall.h
semihost.ld	target/riscv: Set env->bins in gen_exception_illegal	2022-07-03 10:03:20 +10:00
test-div.c	tests/tcg/riscv64: Add test for division	2021-09-01 11:59:12 +10:00
test-noc.S	target/riscv: Set pc_succ_insn for !rvc illegal insn	2023-01-06 10:42:55 +10:00