Peter Maydell 5158de241b target/arm: Implement TT instruction ...

Implement the TT instruction which queries the security
state and access permissions of a memory location.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1512153879-5291-8-git-send-email-peter.maydell@linaro.org

2017-12-13 17:59:24 +00:00

..

alpha

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

arm

target/arm: Implement TT instruction

2017-12-13 17:59:24 +00:00

cris

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

hppa

Capstone disassembler

2017-10-27 08:04:51 +01:00

i386

Miscellaneous bugfixes

2017-11-16 14:42:54 +00:00

lm32

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

m68k

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

microblaze

Capstone disassembler

2017-10-27 08:04:51 +01:00

mips

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

moxie

moxie: cleanup cpu type name composition

2017-10-27 16:03:54 +02:00

nios2

Capstone disassembler

2017-10-27 08:04:51 +01:00

openrisc

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

ppc

target/ppc: Fix system lockups caused by interrupt_request state corruption

2017-12-05 12:28:42 +11:00

s390x

s390x/tcg: fix DIAG 308 with > 1 VCPU (MTTCG)

2017-11-20 09:31:46 +01:00

sh4

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

sparc

linux-user/sparc: Put address for data faults where linux-user expects it

2017-11-07 21:59:18 +02:00

tilegx

tcg: Initialize cpu_env generically

2017-10-24 13:53:42 -07:00

tricore

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

unicore32

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00

xtensa

x86/cpu/numa queue, 2017-10-27

2017-10-30 10:11:22 +00:00