dc488f8880
Rocker is a simulated ethernet switch device. The device supports up to 62
front-panel ports and supports L2 switching and L3 routing functions, as well
as L2/L3/L4 ACLs. The device presents a single PCI device for each switch,
with a memory-mapped register space for device driver access.
Rocker device is invoked with -device, for example a 4-port switch:
-device rocker,name=sw1,len-ports=4,ports[0]=dev0,ports[1]=dev1, \
ports[2]=dev2,ports[3]=dev3
Each port is a netdev and can be paired with using -netdev id=<port name>.
Signed-off-by: Scott Feldman <sfeldma@gmail.com>
Signed-off-by: Jiri Pirko <jiri@resnulli.us>
Acked-by: Scott Feldman <sfeldma@gmail.com>
Acked-by: Jiri Pirko <jiri@resnulli.us>
Signed-off-by: David Ahern <dsahern@gmail.com>
Message-id: 1426306173-24884-7-git-send-email-sfeldma@gmail.com
rocker: fix clang compiler errors
Consolidate all forward typedef declarations to rocker.h.
Signed-off-by: David Ahern <dsahern@gmail.com>
Acked-by: Scott Feldman <sfeldma@gmail.com>
Acked-by: Jiri Pirko <jiri@resnulli.us>
rocker: add support for flow modification
We had support for flow add/del. This adds support for flow mod. I needed
this for L3 support where an existing route is modified using NLM_F_REPLACE.
For example:
ip route add 12.0.0.0/30 nexthop via 11.0.0.1 dev swp1
ip route change 12.0.0.0/30 nexthop via 11.0.0.9 dev swp2
The first cmd adds the route. The second cmd changes the existing route by
changing its nexthop info.
In the device, a mod operation results in the matching flow enty being modified
with the new settings. This is atomic to the device.
Signed-off-by: Scott Feldman <sfeldma@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
492 lines
16 KiB
C
492 lines
16 KiB
C
/*
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* Rocker switch hardware register and descriptor definitions.
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*
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* Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com>
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* Copyright (c) 2014 Jiri Pirko <jiri@resnulli.us>
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*
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*/
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#ifndef _ROCKER_HW_
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#define _ROCKER_HW_
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#define __le16 uint16_t
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#define __le32 uint32_t
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#define __le64 uint64_t
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/*
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* Return codes
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*/
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enum {
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ROCKER_OK = 0,
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ROCKER_ENOENT = 2,
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ROCKER_ENXIO = 6,
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ROCKER_ENOMEM = 12,
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ROCKER_EEXIST = 17,
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ROCKER_EINVAL = 22,
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ROCKER_EMSGSIZE = 90,
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ROCKER_ENOTSUP = 95,
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ROCKER_ENOBUFS = 105,
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};
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/*
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* PCI configuration space
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*/
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#define ROCKER_PCI_REVISION 0x1
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#define ROCKER_PCI_BAR0_IDX 0
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#define ROCKER_PCI_BAR0_SIZE 0x2000
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#define ROCKER_PCI_MSIX_BAR_IDX 1
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#define ROCKER_PCI_MSIX_BAR_SIZE 0x2000
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#define ROCKER_PCI_MSIX_TABLE_OFFSET 0x0000
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#define ROCKER_PCI_MSIX_PBA_OFFSET 0x1000
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/*
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* MSI-X vectors
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*/
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enum {
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ROCKER_MSIX_VEC_CMD,
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ROCKER_MSIX_VEC_EVENT,
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ROCKER_MSIX_VEC_TEST,
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ROCKER_MSIX_VEC_RESERVED0,
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__ROCKER_MSIX_VEC_TX,
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__ROCKER_MSIX_VEC_RX,
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#define ROCKER_MSIX_VEC_TX(port) \
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(__ROCKER_MSIX_VEC_TX + ((port) * 2))
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#define ROCKER_MSIX_VEC_RX(port) \
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(__ROCKER_MSIX_VEC_RX + ((port) * 2))
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#define ROCKER_MSIX_VEC_COUNT(portcnt) \
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(ROCKER_MSIX_VEC_RX((portcnt) - 1) + 1)
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};
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/*
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* Rocker bogus registers
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*/
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#define ROCKER_BOGUS_REG0 0x0000
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#define ROCKER_BOGUS_REG1 0x0004
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#define ROCKER_BOGUS_REG2 0x0008
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#define ROCKER_BOGUS_REG3 0x000c
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/*
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* Rocker test registers
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*/
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#define ROCKER_TEST_REG 0x0010
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#define ROCKER_TEST_REG64 0x0018 /* 8-byte */
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#define ROCKER_TEST_IRQ 0x0020
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#define ROCKER_TEST_DMA_ADDR 0x0028 /* 8-byte */
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#define ROCKER_TEST_DMA_SIZE 0x0030
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#define ROCKER_TEST_DMA_CTRL 0x0034
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/*
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* Rocker test register ctrl
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*/
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#define ROCKER_TEST_DMA_CTRL_CLEAR (1 << 0)
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#define ROCKER_TEST_DMA_CTRL_FILL (1 << 1)
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#define ROCKER_TEST_DMA_CTRL_INVERT (1 << 2)
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/*
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* Rocker DMA ring register offsets
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*/
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#define ROCKER_DMA_DESC_BASE 0x1000
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#define ROCKER_DMA_DESC_SIZE 32
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#define ROCKER_DMA_DESC_MASK 0x1F
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#define ROCKER_DMA_DESC_TOTAL_SIZE \
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(ROCKER_DMA_DESC_SIZE * 64) /* 62 ports + event + cmd */
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#define ROCKER_DMA_DESC_ADDR_OFFSET 0x00 /* 8-byte */
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#define ROCKER_DMA_DESC_SIZE_OFFSET 0x08
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#define ROCKER_DMA_DESC_HEAD_OFFSET 0x0c
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#define ROCKER_DMA_DESC_TAIL_OFFSET 0x10
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#define ROCKER_DMA_DESC_CTRL_OFFSET 0x14
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#define ROCKER_DMA_DESC_CREDITS_OFFSET 0x18
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#define ROCKER_DMA_DESC_RSVD_OFFSET 0x1c
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/*
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* Rocker dma ctrl register bits
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*/
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#define ROCKER_DMA_DESC_CTRL_RESET (1 << 0)
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/*
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* Rocker ring indices
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*/
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#define ROCKER_RING_CMD 0
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#define ROCKER_RING_EVENT 1
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/*
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* Helper macro to do convert a dma ring register
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* to its index. Based on the fact that the register
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* group stride is 32 bytes.
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*/
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#define ROCKER_RING_INDEX(reg) ((reg >> 5) & 0x7F)
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/*
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* Rocker DMA Descriptor
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*/
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typedef struct rocker_desc {
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__le64 buf_addr;
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uint64_t cookie;
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__le16 buf_size;
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__le16 tlv_size;
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__le16 rsvd[5]; /* pad to 32 bytes */
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__le16 comp_err;
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} __attribute__((packed, aligned(8))) RockerDesc;
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/*
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* Rocker TLV type fields
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*/
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typedef struct rocker_tlv {
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__le32 type;
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__le16 len;
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__le16 rsvd;
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} __attribute__((packed, aligned(8))) RockerTlv;
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/* cmd msg */
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enum {
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ROCKER_TLV_CMD_UNSPEC,
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ROCKER_TLV_CMD_TYPE, /* u16 */
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ROCKER_TLV_CMD_INFO, /* nest */
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__ROCKER_TLV_CMD_MAX,
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ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1,
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};
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enum {
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ROCKER_TLV_CMD_TYPE_UNSPEC,
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ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS,
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ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS,
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ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD,
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ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD,
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ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL,
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ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS,
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ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD,
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ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD,
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ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL,
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ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS,
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__ROCKER_TLV_CMD_TYPE_MAX,
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ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1,
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};
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/* cmd info nested for set/get port settings */
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enum {
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ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC,
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ROCKER_TLV_CMD_PORT_SETTINGS_PPORT, /* u32 */
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ROCKER_TLV_CMD_PORT_SETTINGS_SPEED, /* u32 */
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ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX, /* u8 */
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ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG, /* u8 */
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ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR, /* binary */
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ROCKER_TLV_CMD_PORT_SETTINGS_MODE, /* u8 */
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ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING, /* u8 */
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__ROCKER_TLV_CMD_PORT_SETTINGS_MAX,
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ROCKER_TLV_CMD_PORT_SETTINGS_MAX = __ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1,
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};
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enum {
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ROCKER_PORT_MODE_OF_DPA,
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};
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/* event msg */
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enum {
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ROCKER_TLV_EVENT_UNSPEC,
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ROCKER_TLV_EVENT_TYPE, /* u16 */
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ROCKER_TLV_EVENT_INFO, /* nest */
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__ROCKER_TLV_EVENT_MAX,
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ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1,
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};
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enum {
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ROCKER_TLV_EVENT_TYPE_UNSPEC,
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ROCKER_TLV_EVENT_TYPE_LINK_CHANGED,
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ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN,
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__ROCKER_TLV_EVENT_TYPE_MAX,
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ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1,
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};
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/* event info nested for link changed */
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enum {
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ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC,
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ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, /* u32 */
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ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP, /* u8 */
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__ROCKER_TLV_EVENT_LINK_CHANGED_MAX,
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ROCKER_TLV_EVENT_LINK_CHANGED_MAX = __ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1,
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};
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/* event info nested for MAC/VLAN */
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enum {
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ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC,
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ROCKER_TLV_EVENT_MAC_VLAN_PPORT, /* u32 */
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ROCKER_TLV_EVENT_MAC_VLAN_MAC, /* binary */
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ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID, /* __be16 */
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__ROCKER_TLV_EVENT_MAC_VLAN_MAX,
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ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1,
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};
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/* Rx msg */
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enum {
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ROCKER_TLV_RX_UNSPEC,
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ROCKER_TLV_RX_FLAGS, /* u16, see RX_FLAGS_ */
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ROCKER_TLV_RX_CSUM, /* u16 */
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ROCKER_TLV_RX_FRAG_ADDR, /* u64 */
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ROCKER_TLV_RX_FRAG_MAX_LEN, /* u16 */
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ROCKER_TLV_RX_FRAG_LEN, /* u16 */
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__ROCKER_TLV_RX_MAX,
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ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1,
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};
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#define ROCKER_RX_FLAGS_IPV4 (1 << 0)
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#define ROCKER_RX_FLAGS_IPV6 (1 << 1)
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#define ROCKER_RX_FLAGS_CSUM_CALC (1 << 2)
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#define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD (1 << 3)
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#define ROCKER_RX_FLAGS_IP_FRAG (1 << 4)
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#define ROCKER_RX_FLAGS_TCP (1 << 5)
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#define ROCKER_RX_FLAGS_UDP (1 << 6)
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#define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD (1 << 7)
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/* Tx msg */
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enum {
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ROCKER_TLV_TX_UNSPEC,
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ROCKER_TLV_TX_OFFLOAD, /* u8, see TX_OFFLOAD_ */
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ROCKER_TLV_TX_L3_CSUM_OFF, /* u16 */
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ROCKER_TLV_TX_TSO_MSS, /* u16 */
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ROCKER_TLV_TX_TSO_HDR_LEN, /* u16 */
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ROCKER_TLV_TX_FRAGS, /* array */
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__ROCKER_TLV_TX_MAX,
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ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1,
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};
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#define ROCKER_TX_OFFLOAD_NONE 0
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#define ROCKER_TX_OFFLOAD_IP_CSUM 1
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#define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM 2
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#define ROCKER_TX_OFFLOAD_L3_CSUM 3
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#define ROCKER_TX_OFFLOAD_TSO 4
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#define ROCKER_TX_FRAGS_MAX 16
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enum {
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ROCKER_TLV_TX_FRAG_UNSPEC,
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ROCKER_TLV_TX_FRAG, /* nest */
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__ROCKER_TLV_TX_FRAG_MAX,
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ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1,
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};
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enum {
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ROCKER_TLV_TX_FRAG_ATTR_UNSPEC,
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ROCKER_TLV_TX_FRAG_ATTR_ADDR, /* u64 */
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ROCKER_TLV_TX_FRAG_ATTR_LEN, /* u16 */
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__ROCKER_TLV_TX_FRAG_ATTR_MAX,
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ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1,
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};
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/*
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* cmd info nested for OF-DPA msgs
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*/
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enum {
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ROCKER_TLV_OF_DPA_UNSPEC,
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ROCKER_TLV_OF_DPA_TABLE_ID, /* u16 */
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ROCKER_TLV_OF_DPA_PRIORITY, /* u32 */
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ROCKER_TLV_OF_DPA_HARDTIME, /* u32 */
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ROCKER_TLV_OF_DPA_IDLETIME, /* u32 */
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ROCKER_TLV_OF_DPA_COOKIE, /* u64 */
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ROCKER_TLV_OF_DPA_IN_PPORT, /* u32 */
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ROCKER_TLV_OF_DPA_IN_PPORT_MASK, /* u32 */
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ROCKER_TLV_OF_DPA_OUT_PPORT, /* u32 */
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ROCKER_TLV_OF_DPA_GOTO_TABLE_ID, /* u16 */
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ROCKER_TLV_OF_DPA_GROUP_ID, /* u32 */
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ROCKER_TLV_OF_DPA_GROUP_ID_LOWER, /* u32 */
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ROCKER_TLV_OF_DPA_GROUP_COUNT, /* u16 */
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ROCKER_TLV_OF_DPA_GROUP_IDS, /* u32 array */
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ROCKER_TLV_OF_DPA_VLAN_ID, /* __be16 */
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ROCKER_TLV_OF_DPA_VLAN_ID_MASK, /* __be16 */
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ROCKER_TLV_OF_DPA_VLAN_PCP, /* __be16 */
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ROCKER_TLV_OF_DPA_VLAN_PCP_MASK, /* __be16 */
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ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION, /* u8 */
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ROCKER_TLV_OF_DPA_NEW_VLAN_ID, /* __be16 */
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ROCKER_TLV_OF_DPA_NEW_VLAN_PCP, /* u8 */
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ROCKER_TLV_OF_DPA_TUNNEL_ID, /* u32 */
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ROCKER_TLV_OF_DPA_TUNNEL_LPORT, /* u32 */
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ROCKER_TLV_OF_DPA_ETHERTYPE, /* __be16 */
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ROCKER_TLV_OF_DPA_DST_MAC, /* binary */
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ROCKER_TLV_OF_DPA_DST_MAC_MASK, /* binary */
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ROCKER_TLV_OF_DPA_SRC_MAC, /* binary */
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ROCKER_TLV_OF_DPA_SRC_MAC_MASK, /* binary */
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ROCKER_TLV_OF_DPA_IP_PROTO, /* u8 */
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ROCKER_TLV_OF_DPA_IP_PROTO_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_IP_DSCP, /* u8 */
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ROCKER_TLV_OF_DPA_IP_DSCP_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_IP_DSCP_ACTION, /* u8 */
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ROCKER_TLV_OF_DPA_NEW_IP_DSCP, /* u8 */
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ROCKER_TLV_OF_DPA_IP_ECN, /* u8 */
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ROCKER_TLV_OF_DPA_IP_ECN_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_DST_IP, /* __be32 */
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ROCKER_TLV_OF_DPA_DST_IP_MASK, /* __be32 */
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ROCKER_TLV_OF_DPA_SRC_IP, /* __be32 */
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ROCKER_TLV_OF_DPA_SRC_IP_MASK, /* __be32 */
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ROCKER_TLV_OF_DPA_DST_IPV6, /* binary */
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ROCKER_TLV_OF_DPA_DST_IPV6_MASK, /* binary */
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ROCKER_TLV_OF_DPA_SRC_IPV6, /* binary */
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ROCKER_TLV_OF_DPA_SRC_IPV6_MASK, /* binary */
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ROCKER_TLV_OF_DPA_SRC_ARP_IP, /* __be32 */
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ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK, /* __be32 */
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ROCKER_TLV_OF_DPA_L4_DST_PORT, /* __be16 */
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ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK, /* __be16 */
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ROCKER_TLV_OF_DPA_L4_SRC_PORT, /* __be16 */
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ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK, /* __be16 */
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ROCKER_TLV_OF_DPA_ICMP_TYPE, /* u8 */
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ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_ICMP_CODE, /* u8 */
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ROCKER_TLV_OF_DPA_ICMP_CODE_MASK, /* u8 */
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ROCKER_TLV_OF_DPA_IPV6_LABEL, /* __be32 */
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ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK, /* __be32 */
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ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION, /* u8 */
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ROCKER_TLV_OF_DPA_NEW_QUEUE_ID, /* u8 */
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ROCKER_TLV_OF_DPA_CLEAR_ACTIONS, /* u32 */
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ROCKER_TLV_OF_DPA_POP_VLAN, /* u8 */
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ROCKER_TLV_OF_DPA_TTL_CHECK, /* u8 */
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ROCKER_TLV_OF_DPA_COPY_CPU_ACTION, /* u8 */
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__ROCKER_TLV_OF_DPA_MAX,
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ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1,
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};
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/*
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* OF-DPA table IDs
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*/
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enum rocker_of_dpa_table_id {
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ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0,
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ROCKER_OF_DPA_TABLE_ID_VLAN = 10,
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ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20,
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ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30,
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ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40,
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ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50,
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ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60,
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};
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/*
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* OF-DPA flow stats
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*/
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enum {
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ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC,
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ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION, /* u32 */
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ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS, /* u64 */
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ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS, /* u64 */
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__ROCKER_TLV_OF_DPA_FLOW_STAT_MAX,
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ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1,
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};
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/*
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* OF-DPA group types
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*/
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enum rocker_of_dpa_group_type {
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ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0,
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ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE,
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ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST,
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ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST,
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ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD,
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ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE,
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ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST,
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ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP,
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ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY,
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};
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/*
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* OF-DPA group L2 overlay types
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*/
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enum rocker_of_dpa_overlay_type {
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ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0,
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ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST,
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ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST,
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ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST,
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};
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/*
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* OF-DPA group ID encoding
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*/
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#define ROCKER_GROUP_TYPE_SHIFT 28
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#define ROCKER_GROUP_TYPE_MASK 0xf0000000
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#define ROCKER_GROUP_VLAN_ID_SHIFT 16
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#define ROCKER_GROUP_VLAN_ID_MASK 0x0fff0000
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#define ROCKER_GROUP_PORT_SHIFT 0
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#define ROCKER_GROUP_PORT_MASK 0x0000ffff
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#define ROCKER_GROUP_TUNNEL_ID_SHIFT 12
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#define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000
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#define ROCKER_GROUP_SUBTYPE_SHIFT 10
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#define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00
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#define ROCKER_GROUP_INDEX_SHIFT 0
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#define ROCKER_GROUP_INDEX_MASK 0x0000ffff
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#define ROCKER_GROUP_INDEX_LONG_SHIFT 0
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#define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff
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#define ROCKER_GROUP_TYPE_GET(group_id) \
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(((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT)
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#define ROCKER_GROUP_TYPE_SET(type) \
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(((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK)
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#define ROCKER_GROUP_VLAN_GET(group_id) \
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(((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT)
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#define ROCKER_GROUP_VLAN_SET(vlan_id) \
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(((vlan_id) << ROCKER_GROUP_VLAN_ID_SHIFT) & ROCKER_GROUP_VLAN_ID_MASK)
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#define ROCKER_GROUP_PORT_GET(group_id) \
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(((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT)
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#define ROCKER_GROUP_PORT_SET(port) \
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(((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK)
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#define ROCKER_GROUP_INDEX_GET(group_id) \
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(((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT)
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#define ROCKER_GROUP_INDEX_SET(index) \
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(((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK)
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#define ROCKER_GROUP_INDEX_LONG_GET(group_id) \
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(((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \
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ROCKER_GROUP_INDEX_LONG_SHIFT)
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#define ROCKER_GROUP_INDEX_LONG_SET(index) \
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(((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \
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ROCKER_GROUP_INDEX_LONG_MASK)
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#define ROCKER_GROUP_NONE 0
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#define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \
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(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) |\
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ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_PORT_SET(port))
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#define ROCKER_GROUP_L2_REWRITE(index) \
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(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) |\
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ROCKER_GROUP_INDEX_LONG_SET(index))
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#define ROCKER_GROUP_L2_MCAST(vlan_id, index) \
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(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) |\
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ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
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#define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \
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(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) |\
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ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
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#define ROCKER_GROUP_L3_UNICAST(index) \
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(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) |\
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ROCKER_GROUP_INDEX_LONG_SET(index))
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/*
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* Rocker general purpose registers
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*/
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#define ROCKER_CONTROL 0x0300
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#define ROCKER_PORT_PHYS_COUNT 0x0304
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#define ROCKER_PORT_PHYS_LINK_STATUS 0x0310 /* 8-byte */
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#define ROCKER_PORT_PHYS_ENABLE 0x0318 /* 8-byte */
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#define ROCKER_SWITCH_ID 0x0320 /* 8-byte */
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/*
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* Rocker control bits
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*/
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#define ROCKER_CONTROL_RESET (1 << 0)
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#endif /* _ROCKER_HW_ */
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