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Frank Chang 50f6696c0f target/riscv: rvv-1.0: mask-register logical instructions 
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-50-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20 14:51:36 +10:00
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alpha
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arm
target/arm: Correct calculation of tlb range invalidate length
2021-12-15 10:35:26 +00:00
avr
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cris
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hexagon
target/hexagon/cpu.h: don't include qemu-common.h
2021-12-15 10:35:26 +00:00
hppa
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i386
target/i386/kvm: Replace use of __u32 type
2021-12-17 10:40:51 +01:00
m68k
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microblaze
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mips
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nios2
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openrisc
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ppc
PPC64/TCG: Implement 'rfebb' instruction
2021-12-17 17:57:19 +01:00
riscv
target/riscv: rvv-1.0: mask-register logical instructions
2021-12-20 14:51:36 +10:00
rx
target/rx/cpu.h: Don't include qemu-common.h
2021-12-15 10:35:26 +00:00
s390x
s390: kvm: adjust diag318 resets to retain data
2021-12-17 09:12:37 +01:00
sh4
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sparc
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tricore
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xtensa
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Kconfig
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meson.build
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