Richard Henderson 50a7470e3e target/arm: Improve vector REV ... We can eliminate the requirement for a zero-extended output, because the following store will ignore any garbage high bits. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2021-06-29 10:04:57 -07:00
..
alpha	target/alpha: Honor the FEN bit	2021-06-28 07:27:55 -07:00
arm	target/arm: Improve vector REV	2021-06-29 10:04:57 -07:00
avr	target/avr: Convert to TranslatorOps	2021-06-29 10:04:56 -07:00
cris	target/cris: Do not exit tb for X_FLAG changes	2021-06-29 10:04:56 -07:00
hexagon	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
hppa	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
i386	tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64	2021-06-29 10:04:57 -07:00
m68k	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
microblaze	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
mips	tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64	2021-06-29 10:04:57 -07:00
nios2	target/nios2: Use pc_next for pc + 4	2021-06-29 10:03:11 -07:00
openrisc	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
ppc	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
riscv	target/riscv: gdbstub: Fix dynamic CSR XML generation	2021-06-24 05:00:12 -07:00
rx	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
s390x	tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64	2021-06-29 10:04:57 -07:00
sh4	tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64	2021-06-29 10:04:57 -07:00
sparc	docs: fix references to docs/devel/tracing.rst	2021-06-02 06:51:09 +02:00
tricore	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
xtensa	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
meson.build	Drop the deprecated unicore32 target	2021-05-12 18:20:52 +02:00