Philippe Mathieu-Daudé 04bc302758 target/riscv/cpu: Move Floating-Point fields closer ...

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221217172907.8364-7-philmd@linaro.org>

2023-02-27 22:29:01 +01:00

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insn_trans

target/riscv: fix ctzw behavior

2023-02-07 08:19:23 +10:00

arch_dump.c

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bitmanip_helper.c

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common-semi-target.h

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cpu_bits.h

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cpu_helper.c

target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()

2023-02-23 14:21:33 -08:00

cpu_user.h

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cpu_vendorid.h

RISC-V: Add initial support for T-Head C906

2023-02-07 08:19:23 +10:00

cpu-param.h

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cpu.c

target/riscv: Remove privileged spec version restriction for RVV

2023-02-23 14:21:31 -08:00

cpu.h

target/riscv/cpu: Move Floating-Point fields closer

2023-02-27 22:29:01 +01:00

crypto_helper.c

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csr.c

target/riscv: Remove privileged spec version restriction for RVV

2023-02-23 14:21:31 -08:00

debug.c

target/riscv: set tval for triggered watchpoints

2023-02-07 08:19:23 +10:00

debug.h

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fpu_helper.c

target/riscv: Remove helper_set_rod_rounding_mode

2023-01-20 10:14:14 +10:00

gdbstub.c

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helper.h

RISC-V: Adding XTheadSync ISA extension

2023-02-07 08:19:23 +10:00

insn16.decode

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insn32.decode

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instmap.h

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internals.h

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Kconfig

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kvm_riscv.h

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kvm-stub.c

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kvm.c

target/riscv: fix SBI getchar handler for KVM

2023-02-07 08:19:23 +10:00

m128_helper.c

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machine.c

hw/char: riscv_htif: Move registers from CPUArchState to HTIFState

2023-01-20 10:14:13 +10:00

meson.build

RISC-V: Adding XTheadCmo ISA extension

2023-02-07 08:19:23 +10:00

monitor.c

bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx

2023-01-18 11:14:34 +01:00

op_helper.c

RISC-V: Adding XTheadSync ISA extension

2023-02-07 08:19:23 +10:00

pmp.c

target/riscv: Smepmp: Skip applying default rules when address matches

2023-02-23 14:21:32 -08:00

pmp.h

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pmu.c

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pmu.h

riscv: Clean up includes

2023-02-08 07:28:05 +01:00

sbi_ecall_interface.h

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time_helper.c

target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX

2023-02-07 08:19:23 +10:00

time_helper.h

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trace-events

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trace.h

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translate.c

target/riscv: fix for virtual instr exception

2023-02-07 08:19:23 +10:00

vector_helper.c

target/riscv: Fix vslide1up.vf and vslide1down.vf

2023-02-23 14:21:34 -08:00

xthead.decode

RISC-V: Adding XTheadFmv ISA extension

2023-02-07 08:19:23 +10:00

XVentanaCondOps.decode

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