112a829f8f
Currently our PL080/PL081 model uses a combination of the CPU's
address space (via cpu_physical_memory_{read,write}()) and the
system address space for performing DMA accesses.
For the PL081s in the MPS FPGA images, their DMA accesses
must go via Master Security Controllers. Switch the
PL080/PL081 model to take a MemoryRegion property which
defines its downstream for making DMA accesses.
Since the PL08x are only used in two board models, we
make provision of the 'downstream' link mandatory and convert
both users at once, rather than having it be optional with
a default to the system address space.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/*
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* ARM PrimeCell PL080/PL081 DMA controller
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*
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* Copyright (c) 2006 CodeSourcery.
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* Copyright (c) 2018 Linaro Limited
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* Written by Paul Brook, Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
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* The PL080 TRM is:
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* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf
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* and the PL081 TRM is:
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* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf
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*
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* QEMU interface:
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* + sysbus IRQ 0: DMACINTR combined interrupt line
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* + sysbus IRQ 1: DMACINTERR error interrupt request
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* + sysbus IRQ 2: DMACINTTC count interrupt request
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* + sysbus MMIO region 0: MemoryRegion for the device's registers
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* + QOM property "downstream": MemoryRegion defining where DMA
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* bus master transactions are made
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*/
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#ifndef HW_DMA_PL080_H
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#define HW_DMA_PL080_H
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#include "hw/sysbus.h"
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#define PL080_MAX_CHANNELS 8
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typedef struct {
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uint32_t src;
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uint32_t dest;
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uint32_t lli;
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uint32_t ctrl;
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uint32_t conf;
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} pl080_channel;
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#define TYPE_PL080 "pl080"
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#define TYPE_PL081 "pl081"
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#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
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typedef struct PL080State {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint8_t tc_int;
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uint8_t tc_mask;
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uint8_t err_int;
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uint8_t err_mask;
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uint32_t conf;
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uint32_t sync;
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uint32_t req_single;
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uint32_t req_burst;
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pl080_channel chan[PL080_MAX_CHANNELS];
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int nchannels;
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/* Flag to avoid recursive DMA invocations. */
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int running;
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qemu_irq irq;
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qemu_irq interr;
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qemu_irq inttc;
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MemoryRegion *downstream;
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AddressSpace downstream_as;
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} PL080State;
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#endif
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