502700d067
We should avoid including the whole of softfloat headers in cpu.h and explicitly include it only where we will be calling softfloat functions. We can use the -types.h in cpu.h for the few bits that are global. We also move the restore_snan_bit_mode into internal.h and include -helpers.h there. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
445 lines
14 KiB
C
445 lines
14 KiB
C
/* mips internal definitions and helpers
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef MIPS_INTERNAL_H
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#define MIPS_INTERNAL_H
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#include "fpu/softfloat-helpers.h"
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/* MMU types, the first four entries have the same layout as the
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CP0C0_MT field. */
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enum mips_mmu_types {
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MMU_TYPE_NONE,
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MMU_TYPE_R4000,
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MMU_TYPE_RESERVED,
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MMU_TYPE_FMT,
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MMU_TYPE_R3000,
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MMU_TYPE_R6000,
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MMU_TYPE_R8000
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};
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struct mips_def_t {
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const char *name;
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int32_t CP0_PRid;
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int32_t CP0_Config0;
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int32_t CP0_Config1;
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int32_t CP0_Config2;
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int32_t CP0_Config3;
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int32_t CP0_Config4;
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int32_t CP0_Config4_rw_bitmask;
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int32_t CP0_Config5;
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int32_t CP0_Config5_rw_bitmask;
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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target_ulong CP0_LLAddr_rw_bitmask;
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int CP0_LLAddr_shift;
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int32_t SYNCI_Step;
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int32_t CCRes;
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int32_t CP0_Status_rw_bitmask;
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int32_t CP0_TCStatus_rw_bitmask;
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int32_t CP0_SRSCtl;
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int32_t CP1_fcr0;
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int32_t CP1_fcr31_rw_bitmask;
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int32_t CP1_fcr31;
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int32_t MSAIR;
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int32_t SEGBITS;
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int32_t PABITS;
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int32_t CP0_SRSConf0_rw_bitmask;
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int32_t CP0_SRSConf0;
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int32_t CP0_SRSConf1_rw_bitmask;
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int32_t CP0_SRSConf1;
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int32_t CP0_SRSConf2_rw_bitmask;
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int32_t CP0_SRSConf2;
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int32_t CP0_SRSConf3_rw_bitmask;
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int32_t CP0_SRSConf3;
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int32_t CP0_SRSConf4_rw_bitmask;
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int32_t CP0_SRSConf4;
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int32_t CP0_PageGrain_rw_bitmask;
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int32_t CP0_PageGrain;
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target_ulong CP0_EBaseWG_rw_bitmask;
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uint64_t insn_flags;
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enum mips_mmu_types mmu_type;
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int32_t SAARP;
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};
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extern const struct mips_def_t mips_defs[];
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extern const int mips_defs_number;
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enum CPUMIPSMSADataFormat {
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DF_BYTE = 0,
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DF_HALF,
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DF_WORD,
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DF_DOUBLE
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};
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void mips_cpu_do_interrupt(CPUState *cpu);
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bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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#if !defined(CONFIG_USER_ONLY)
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typedef struct r4k_tlb_t r4k_tlb_t;
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struct r4k_tlb_t {
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target_ulong VPN;
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uint32_t PageMask;
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uint16_t ASID;
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unsigned int G:1;
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unsigned int C0:3;
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unsigned int C1:3;
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unsigned int V0:1;
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unsigned int V1:1;
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unsigned int D0:1;
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unsigned int D1:1;
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unsigned int XI0:1;
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unsigned int XI1:1;
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unsigned int RI0:1;
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unsigned int RI1:1;
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unsigned int EHINV:1;
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uint64_t PFN[2];
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};
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struct CPUMIPSTLBContext {
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uint32_t nb_tlb;
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uint32_t tlb_in_use;
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int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type);
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void (*helper_tlbwi)(struct CPUMIPSState *env);
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void (*helper_tlbwr)(struct CPUMIPSState *env);
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void (*helper_tlbp)(struct CPUMIPSState *env);
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void (*helper_tlbr)(struct CPUMIPSState *env);
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void (*helper_tlbinv)(struct CPUMIPSState *env);
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void (*helper_tlbinvf)(struct CPUMIPSState *env);
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union {
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struct {
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r4k_tlb_t tlb[MIPS_TLB_MAX];
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} r4k;
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} mmu;
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};
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int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type);
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int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type);
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int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type);
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void r4k_helper_tlbwi(CPUMIPSState *env);
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void r4k_helper_tlbwr(CPUMIPSState *env);
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void r4k_helper_tlbp(CPUMIPSState *env);
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void r4k_helper_tlbr(CPUMIPSState *env);
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void r4k_helper_tlbinv(CPUMIPSState *env);
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void r4k_helper_tlbinvf(CPUMIPSState *env);
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void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
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void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
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bool is_write, bool is_exec, int unused,
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unsigned size);
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hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
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int rw);
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#endif
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#define cpu_signal_handler cpu_mips_signal_handler
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#ifndef CONFIG_USER_ONLY
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extern const VMStateDescription vmstate_mips_cpu;
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#endif
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static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
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{
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return (env->CP0_Status & (1 << CP0St_IE)) &&
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!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM) &&
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/* Note that the TCStatus IXMT field is initialized to zero,
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and only MT capable cores can set it to one. So we don't
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need to check for MT capabilities here. */
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!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
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}
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/* Check if there is pending and not masked out interrupt */
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static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
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{
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int32_t pending;
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int32_t status;
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bool r;
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pending = env->CP0_Cause & CP0Ca_IP_mask;
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status = env->CP0_Status & CP0Ca_IP_mask;
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if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
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/* A MIPS configured with a vectorizing external interrupt controller
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will feed a vector into the Cause pending lines. The core treats
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the status lines as a vector level, not as indiviual masks. */
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r = pending > status;
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} else {
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/* A MIPS configured with compatibility or VInt (Vectored Interrupts)
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treats the pending lines as individual interrupt lines, the status
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lines are individual masks. */
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r = (pending & status) != 0;
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}
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return r;
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}
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void mips_tcg_init(void);
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/* TODO QOM'ify CPU reset and remove */
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void cpu_state_reset(CPUMIPSState *s);
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void cpu_mips_realize_env(CPUMIPSState *env);
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/* cp0_timer.c */
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uint32_t cpu_mips_get_random(CPUMIPSState *env);
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uint32_t cpu_mips_get_count(CPUMIPSState *env);
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void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
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void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
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void cpu_mips_start_count(CPUMIPSState *env);
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void cpu_mips_stop_count(CPUMIPSState *env);
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/* helper.c */
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bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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/* op_helper.c */
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uint32_t float_class_s(uint32_t arg, float_status *fst);
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uint64_t float_class_d(uint64_t arg, float_status *fst);
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extern unsigned int ieee_rm[];
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int ieee_ex_to_mips(int xcpt);
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void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
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static inline void restore_rounding_mode(CPUMIPSState *env)
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{
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set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
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&env->active_fpu.fp_status);
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}
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static inline void restore_flush_mode(CPUMIPSState *env)
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{
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set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
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&env->active_fpu.fp_status);
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}
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static inline void restore_snan_bit_mode(CPUMIPSState *env)
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{
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set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
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&env->active_fpu.fp_status);
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}
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static inline void restore_fp_status(CPUMIPSState *env)
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{
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restore_rounding_mode(env);
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restore_flush_mode(env);
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restore_snan_bit_mode(env);
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}
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static inline void restore_msa_fp_status(CPUMIPSState *env)
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{
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float_status *status = &env->active_tc.msa_fp_status;
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int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
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bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
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set_float_rounding_mode(ieee_rm[rounding_mode], status);
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set_flush_to_zero(flush_to_zero, status);
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set_flush_inputs_to_zero(flush_to_zero, status);
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}
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static inline void restore_pamask(CPUMIPSState *env)
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{
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if (env->hflags & MIPS_HFLAG_ELPA) {
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env->PAMask = (1ULL << env->PABITS) - 1;
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} else {
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env->PAMask = PAMASK_BASE;
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}
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}
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static inline int mips_vpe_active(CPUMIPSState *env)
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{
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int active = 1;
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/* Check that the VPE is enabled. */
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if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
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active = 0;
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}
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/* Check that the VPE is activated. */
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if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
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active = 0;
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}
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/* Now verify that there are active thread contexts in the VPE.
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This assumes the CPU model will internally reschedule threads
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if the active one goes to sleep. If there are no threads available
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the active one will be in a sleeping state, and we can turn off
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the entire VPE. */
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if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
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/* TC is not activated. */
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active = 0;
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}
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if (env->active_tc.CP0_TCHalt & 1) {
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/* TC is in halt state. */
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active = 0;
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}
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return active;
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}
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static inline int mips_vp_active(CPUMIPSState *env)
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{
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CPUState *other_cs = first_cpu;
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/* Check if the VP disabled other VPs (which means the VP is enabled) */
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if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
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return 1;
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}
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/* Check if the virtual processor is disabled due to a DVP */
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CPU_FOREACH(other_cs) {
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MIPSCPU *other_cpu = MIPS_CPU(other_cs);
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if ((&other_cpu->env != env) &&
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((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
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return 0;
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}
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}
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return 1;
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}
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static inline void compute_hflags(CPUMIPSState *env)
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{
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env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
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MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
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MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
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MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
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MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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env->hflags |= MIPS_HFLAG_ERL;
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}
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if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
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!(env->CP0_Status & (1 << CP0St_ERL)) &&
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!(env->hflags & MIPS_HFLAG_DM)) {
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env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
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}
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#if defined(TARGET_MIPS64)
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if ((env->insn_flags & ISA_MIPS3) &&
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(((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
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(env->CP0_Status & (1 << CP0St_PX)) ||
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(env->CP0_Status & (1 << CP0St_UX)))) {
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env->hflags |= MIPS_HFLAG_64;
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}
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if (!(env->insn_flags & ISA_MIPS3)) {
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env->hflags |= MIPS_HFLAG_AWRAP;
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} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
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!(env->CP0_Status & (1 << CP0St_UX))) {
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env->hflags |= MIPS_HFLAG_AWRAP;
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} else if (env->insn_flags & ISA_MIPS64R6) {
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/* Address wrapping for Supervisor and Kernel is specified in R6 */
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if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
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!(env->CP0_Status & (1 << CP0St_SX))) ||
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(((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
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!(env->CP0_Status & (1 << CP0St_KX)))) {
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env->hflags |= MIPS_HFLAG_AWRAP;
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}
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}
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#endif
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if (((env->CP0_Status & (1 << CP0St_CU0)) &&
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!(env->insn_flags & ISA_MIPS32R6)) ||
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!(env->hflags & MIPS_HFLAG_KSU)) {
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env->hflags |= MIPS_HFLAG_CP0;
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}
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if (env->CP0_Status & (1 << CP0St_CU1)) {
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env->hflags |= MIPS_HFLAG_FPU;
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}
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if (env->CP0_Status & (1 << CP0St_FR)) {
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env->hflags |= MIPS_HFLAG_F64;
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}
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if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
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(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
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env->hflags |= MIPS_HFLAG_SBRI;
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}
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if (env->insn_flags & ASE_DSP_R3) {
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/*
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* Our cpu supports DSP R3 ASE, so enable
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* access to DSP R3 resources.
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*/
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if (env->CP0_Status & (1 << CP0St_MX)) {
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env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
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MIPS_HFLAG_DSP_R3;
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}
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} else if (env->insn_flags & ASE_DSP_R2) {
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/*
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* Our cpu supports DSP R2 ASE, so enable
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* access to DSP R2 resources.
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*/
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if (env->CP0_Status & (1 << CP0St_MX)) {
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env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
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}
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} else if (env->insn_flags & ASE_DSP) {
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/*
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* Our cpu supports DSP ASE, so enable
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* access to DSP resources.
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*/
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if (env->CP0_Status & (1 << CP0St_MX)) {
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env->hflags |= MIPS_HFLAG_DSP;
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}
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}
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if (env->insn_flags & ISA_MIPS32R2) {
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if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
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env->hflags |= MIPS_HFLAG_COP1X;
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}
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} else if (env->insn_flags & ISA_MIPS32) {
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if (env->hflags & MIPS_HFLAG_64) {
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env->hflags |= MIPS_HFLAG_COP1X;
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}
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} else if (env->insn_flags & ISA_MIPS4) {
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/* All supported MIPS IV CPUs use the XX (CU3) to enable
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and disable the MIPS IV extensions to the MIPS III ISA.
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Some other MIPS IV CPUs ignore the bit, so the check here
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would be too restrictive for them. */
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if (env->CP0_Status & (1U << CP0St_CU3)) {
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env->hflags |= MIPS_HFLAG_COP1X;
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}
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}
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if (env->insn_flags & ASE_MSA) {
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if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
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env->hflags |= MIPS_HFLAG_MSA;
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}
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}
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if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
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if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
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env->hflags |= MIPS_HFLAG_FRE;
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}
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}
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if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
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if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
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env->hflags |= MIPS_HFLAG_ELPA;
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}
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}
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}
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void cpu_mips_tlb_flush(CPUMIPSState *env);
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
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void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
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int error_code, uintptr_t pc);
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static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
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uint32_t exception,
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uintptr_t pc)
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{
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do_raise_exception_err(env, exception, 0, pc);
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}
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#endif
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