4fe0e9db0a
Compute all carry bits in parallel instead of a loop. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
563 lines
16 KiB
PHP
563 lines
16 KiB
PHP
/*
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* Power ISA decode for Fixed-Point Facility instructions
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*
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* Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Fixed-Point Load/Store Instructions
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*/
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static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
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bool store, MemOp mop)
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{
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TCGv ea;
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if (update && (ra == 0 || (!store && ra == rt))) {
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gen_invalid(ctx);
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return true;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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ea = do_ea_calc(ctx, ra, displ);
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mop ^= ctx->default_tcg_memop_mask;
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if (store) {
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tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
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} else {
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tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
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}
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if (update) {
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tcg_gen_mov_tl(cpu_gpr[ra], ea);
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}
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return true;
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}
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static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
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MemOp mop)
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{
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return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
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}
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static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
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bool store, MemOp mop)
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{
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arg_D d;
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if (!resolve_PLS_D(ctx, &d, a)) {
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return true;
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}
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return do_ldst_D(ctx, &d, update, store, mop);
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}
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static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
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bool store, MemOp mop)
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{
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return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
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}
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static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
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{
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#if defined(TARGET_PPC64)
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TCGv ea;
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TCGv_i64 low_addr_gpr, high_addr_gpr;
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MemOp mop;
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REQUIRE_INSNS_FLAGS(ctx, 64BX);
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if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
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/* lq and stq were privileged prior to V. 2.07 */
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REQUIRE_SV(ctx);
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if (ctx->le_mode) {
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gen_align_no_le(ctx);
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return true;
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}
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}
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if (!store && unlikely(a->ra == a->rt)) {
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gen_invalid(ctx);
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return true;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si));
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if (prefixed || !ctx->le_mode) {
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low_addr_gpr = cpu_gpr[a->rt];
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high_addr_gpr = cpu_gpr[a->rt + 1];
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} else {
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low_addr_gpr = cpu_gpr[a->rt + 1];
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high_addr_gpr = cpu_gpr[a->rt];
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}
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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if (HAVE_ATOMIC128) {
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mop = DEF_MEMOP(MO_128);
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TCGv_i32 oi = tcg_constant_i32(make_memop_idx(mop, ctx->mem_idx));
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if (store) {
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if (ctx->le_mode) {
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gen_helper_stq_le_parallel(cpu_env, ea, low_addr_gpr,
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high_addr_gpr, oi);
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} else {
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gen_helper_stq_be_parallel(cpu_env, ea, high_addr_gpr,
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low_addr_gpr, oi);
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}
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} else {
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if (ctx->le_mode) {
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gen_helper_lq_le_parallel(low_addr_gpr, cpu_env, ea, oi);
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tcg_gen_ld_i64(high_addr_gpr, cpu_env,
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offsetof(CPUPPCState, retxh));
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} else {
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gen_helper_lq_be_parallel(high_addr_gpr, cpu_env, ea, oi);
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tcg_gen_ld_i64(low_addr_gpr, cpu_env,
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offsetof(CPUPPCState, retxh));
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}
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}
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} else {
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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} else {
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mop = DEF_MEMOP(MO_UQ);
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if (store) {
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tcg_gen_qemu_st_i64(low_addr_gpr, ea, ctx->mem_idx, mop);
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} else {
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tcg_gen_qemu_ld_i64(low_addr_gpr, ea, ctx->mem_idx, mop);
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}
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gen_addr_add(ctx, ea, ea, 8);
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if (store) {
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tcg_gen_qemu_st_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
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} else {
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tcg_gen_qemu_ld_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
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}
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}
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#else
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qemu_build_not_reached();
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#endif
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return true;
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}
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static bool do_ldst_quad_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
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{
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arg_D d;
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if (!resolve_PLS_D(ctx, &d, a)) {
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return true;
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}
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return do_ldst_quad(ctx, &d, store, true);
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}
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/* Load Byte and Zero */
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TRANS(LBZ, do_ldst_D, false, false, MO_UB)
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TRANS(LBZX, do_ldst_X, false, false, MO_UB)
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TRANS(LBZU, do_ldst_D, true, false, MO_UB)
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TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
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TRANS(PLBZ, do_ldst_PLS_D, false, false, MO_UB)
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/* Load Halfword and Zero */
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TRANS(LHZ, do_ldst_D, false, false, MO_UW)
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TRANS(LHZX, do_ldst_X, false, false, MO_UW)
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TRANS(LHZU, do_ldst_D, true, false, MO_UW)
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TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
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TRANS(PLHZ, do_ldst_PLS_D, false, false, MO_UW)
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/* Load Halfword Algebraic */
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TRANS(LHA, do_ldst_D, false, false, MO_SW)
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TRANS(LHAX, do_ldst_X, false, false, MO_SW)
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TRANS(LHAU, do_ldst_D, true, false, MO_SW)
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TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
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TRANS(PLHA, do_ldst_PLS_D, false, false, MO_SW)
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/* Load Word and Zero */
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TRANS(LWZ, do_ldst_D, false, false, MO_UL)
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TRANS(LWZX, do_ldst_X, false, false, MO_UL)
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TRANS(LWZU, do_ldst_D, true, false, MO_UL)
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TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
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TRANS(PLWZ, do_ldst_PLS_D, false, false, MO_UL)
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/* Load Word Algebraic */
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TRANS64(LWA, do_ldst_D, false, false, MO_SL)
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TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
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TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
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TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL)
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/* Load Doubleword */
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TRANS64(LD, do_ldst_D, false, false, MO_UQ)
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TRANS64(LDX, do_ldst_X, false, false, MO_UQ)
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TRANS64(LDU, do_ldst_D, true, false, MO_UQ)
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TRANS64(LDUX, do_ldst_X, true, false, MO_UQ)
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TRANS64(PLD, do_ldst_PLS_D, false, false, MO_UQ)
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/* Load Quadword */
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TRANS64(LQ, do_ldst_quad, false, false);
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TRANS64(PLQ, do_ldst_quad_PLS_D, false);
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/* Store Byte */
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TRANS(STB, do_ldst_D, false, true, MO_UB)
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TRANS(STBX, do_ldst_X, false, true, MO_UB)
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TRANS(STBU, do_ldst_D, true, true, MO_UB)
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TRANS(STBUX, do_ldst_X, true, true, MO_UB)
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TRANS(PSTB, do_ldst_PLS_D, false, true, MO_UB)
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/* Store Halfword */
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TRANS(STH, do_ldst_D, false, true, MO_UW)
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TRANS(STHX, do_ldst_X, false, true, MO_UW)
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TRANS(STHU, do_ldst_D, true, true, MO_UW)
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TRANS(STHUX, do_ldst_X, true, true, MO_UW)
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TRANS(PSTH, do_ldst_PLS_D, false, true, MO_UW)
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/* Store Word */
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TRANS(STW, do_ldst_D, false, true, MO_UL)
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TRANS(STWX, do_ldst_X, false, true, MO_UL)
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TRANS(STWU, do_ldst_D, true, true, MO_UL)
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TRANS(STWUX, do_ldst_X, true, true, MO_UL)
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TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL)
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/* Store Doubleword */
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TRANS64(STD, do_ldst_D, false, true, MO_UQ)
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TRANS64(STDX, do_ldst_X, false, true, MO_UQ)
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TRANS64(STDU, do_ldst_D, true, true, MO_UQ)
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TRANS64(STDUX, do_ldst_X, true, true, MO_UQ)
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TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_UQ)
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/* Store Quadword */
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TRANS64(STQ, do_ldst_quad, true, false);
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TRANS64(PSTQ, do_ldst_quad_PLS_D, true);
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/*
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* Fixed-Point Compare Instructions
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*/
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static bool do_cmp_X(DisasContext *ctx, arg_X_bfl *a, bool s)
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{
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if ((ctx->insns_flags & PPC_64B) == 0) {
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/*
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* For 32-bit implementations, The Programming Environments Manual says
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* that "the L field must be cleared, otherwise the instruction form is
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* invalid." It seems, however, that most 32-bit CPUs ignore invalid
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* forms (e.g., section "Instruction Formats" of the 405 and 440
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* manuals, "Integer Compare Instructions" of the 601 manual), with the
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* notable exception of the e500 and e500mc, where L=1 was reported to
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* cause an exception.
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*/
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if (a->l) {
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if ((ctx->insns_flags2 & PPC2_BOOKE206)) {
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/*
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* For 32-bit Book E v2.06 implementations (i.e. e500/e500mc),
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* generate an illegal instruction exception.
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*/
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return false;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Invalid form of CMP%s at 0x" TARGET_FMT_lx ", L = 1\n",
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s ? "" : "L", ctx->cia);
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}
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}
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gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
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return true;
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}
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/* For 64-bit implementations, deal with bit L accordingly. */
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if (a->l) {
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gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
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} else {
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gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
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}
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return true;
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}
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static bool do_cmp_D(DisasContext *ctx, arg_D_bf *a, bool s)
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{
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if ((ctx->insns_flags & PPC_64B) == 0) {
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/*
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* For 32-bit implementations, The Programming Environments Manual says
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* that "the L field must be cleared, otherwise the instruction form is
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* invalid." It seems, however, that most 32-bit CPUs ignore invalid
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* forms (e.g., section "Instruction Formats" of the 405 and 440
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* manuals, "Integer Compare Instructions" of the 601 manual), with the
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* notable exception of the e500 and e500mc, where L=1 was reported to
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* cause an exception.
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*/
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if (a->l) {
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if ((ctx->insns_flags2 & PPC2_BOOKE206)) {
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/*
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* For 32-bit Book E v2.06 implementations (i.e. e500/e500mc),
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* generate an illegal instruction exception.
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*/
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return false;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Invalid form of CMP%s at 0x" TARGET_FMT_lx ", L = 1\n",
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s ? "I" : "LI", ctx->cia);
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}
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}
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gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
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return true;
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}
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/* For 64-bit implementations, deal with bit L accordingly. */
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if (a->l) {
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gen_op_cmp(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
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} else {
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gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
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}
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return true;
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}
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TRANS(CMP, do_cmp_X, true);
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TRANS(CMPL, do_cmp_X, false);
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TRANS(CMPI, do_cmp_D, true);
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TRANS(CMPLI, do_cmp_D, false);
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/*
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* Fixed-Point Arithmetic Instructions
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*/
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static bool trans_ADDI(DisasContext *ctx, arg_D *a)
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{
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if (a->ra) {
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tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
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} else {
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tcg_gen_movi_tl(cpu_gpr[a->rt], a->si);
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}
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return true;
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}
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static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a)
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{
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arg_D d;
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if (!resolve_PLS_D(ctx, &d, a)) {
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return true;
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}
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return trans_ADDI(ctx, &d);
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}
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static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
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{
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a->si <<= 16;
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return trans_ADDI(ctx, a);
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}
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static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
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{
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REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d << 16));
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return true;
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}
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static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
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{
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gen_invalid(ctx);
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return true;
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}
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static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
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{
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return true;
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}
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static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
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{
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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uint32_t mask = 0x08 >> (a->bi & 0x03);
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TCGCond cond = rev ? TCG_COND_EQ : TCG_COND_NE;
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TCGv temp = tcg_temp_new();
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tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
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tcg_gen_andi_tl(temp, temp, mask);
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tcg_gen_setcondi_tl(cond, cpu_gpr[a->rt], temp, 0);
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if (neg) {
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tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]);
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}
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return true;
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}
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TRANS(SETBC, do_set_bool_cond, false, false)
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TRANS(SETBCR, do_set_bool_cond, false, true)
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TRANS(SETNBC, do_set_bool_cond, true, false)
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TRANS(SETNBCR, do_set_bool_cond, true, true)
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static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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#if defined(TARGET_PPC64)
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gen_helper_CFUGED(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
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#else
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qemu_build_not_reached();
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#endif
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return true;
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}
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static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, int64_t trail)
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{
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TCGv_i64 t0, t1;
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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tcg_gen_and_i64(t0, src, mask);
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if (trail) {
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tcg_gen_ctzi_i64(t0, t0, -1);
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} else {
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tcg_gen_clzi_i64(t0, t0, -1);
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}
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tcg_gen_setcondi_i64(TCG_COND_NE, t1, t0, -1);
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tcg_gen_andi_i64(t0, t0, 63);
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tcg_gen_xori_i64(t0, t0, 63);
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if (trail) {
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tcg_gen_shl_i64(t0, mask, t0);
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tcg_gen_shl_i64(t0, t0, t1);
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} else {
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tcg_gen_shr_i64(t0, mask, t0);
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tcg_gen_shr_i64(t0, t0, t1);
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}
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tcg_gen_ctpop_i64(dst, t0);
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}
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static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
|
|
{
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REQUIRE_64BIT(ctx);
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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#if defined(TARGET_PPC64)
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do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], false);
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#else
|
|
qemu_build_not_reached();
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#endif
|
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return true;
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|
}
|
|
|
|
static bool trans_CNTTZDM(DisasContext *ctx, arg_X *a)
|
|
{
|
|
REQUIRE_64BIT(ctx);
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
|
|
#if defined(TARGET_PPC64)
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|
do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], true);
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#else
|
|
qemu_build_not_reached();
|
|
#endif
|
|
return true;
|
|
}
|
|
|
|
static bool trans_PDEPD(DisasContext *ctx, arg_X *a)
|
|
{
|
|
REQUIRE_64BIT(ctx);
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|
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
|
|
#if defined(TARGET_PPC64)
|
|
gen_helper_PDEPD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
|
|
#else
|
|
qemu_build_not_reached();
|
|
#endif
|
|
return true;
|
|
}
|
|
|
|
static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
|
|
{
|
|
REQUIRE_64BIT(ctx);
|
|
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
|
|
#if defined(TARGET_PPC64)
|
|
gen_helper_PEXTD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
|
|
#else
|
|
qemu_build_not_reached();
|
|
#endif
|
|
return true;
|
|
}
|
|
|
|
static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
|
|
{
|
|
const target_ulong carry_bits = (target_ulong)-1 / 0xf;
|
|
TCGv in1, in2, carryl, carryh, tmp;
|
|
TCGv zero = tcg_constant_tl(0);
|
|
|
|
REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
|
|
|
|
in1 = cpu_gpr[a->ra];
|
|
in2 = cpu_gpr[a->rb];
|
|
tmp = tcg_temp_new();
|
|
carryl = tcg_temp_new();
|
|
carryh = tcg_temp_new();
|
|
|
|
/* Addition with carry. */
|
|
tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero);
|
|
/* Addition without carry. */
|
|
tcg_gen_xor_tl(tmp, in1, in2);
|
|
/* Difference between the two is carry in to each bit. */
|
|
tcg_gen_xor_tl(carryl, carryl, tmp);
|
|
|
|
/*
|
|
* The carry-out that we're looking for is the carry-in to
|
|
* the next nibble. Shift the double-word down one nibble,
|
|
* which puts all of the bits back into one word.
|
|
*/
|
|
tcg_gen_extract2_tl(carryl, carryl, carryh, 4);
|
|
|
|
/* Invert, isolate the carry bits, and produce 6's. */
|
|
tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl);
|
|
tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
|
|
return true;
|
|
}
|
|
|
|
static bool trans_CDTBCD(DisasContext *ctx, arg_X_sa *a)
|
|
{
|
|
REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
|
|
gen_helper_CDTBCD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
|
|
return true;
|
|
}
|
|
|
|
static bool trans_CBCDTD(DisasContext *ctx, arg_X_sa *a)
|
|
{
|
|
REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
|
|
gen_helper_CBCDTD(cpu_gpr[a->ra], cpu_gpr[a->rs]);
|
|
return true;
|
|
}
|
|
|
|
static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,
|
|
void (*helper)(TCGv_ptr, TCGv, TCGv, TCGv))
|
|
{
|
|
TCGv ea;
|
|
|
|
if (!(ctx->insns_flags2 & PPC2_ISA310)) {
|
|
/* if version is before v3.1, this operation is a nop */
|
|
return true;
|
|
}
|
|
|
|
if (priv) {
|
|
/* if instruction is privileged but the context is in user space */
|
|
REQUIRE_SV(ctx);
|
|
}
|
|
|
|
if (unlikely(a->ra == 0)) {
|
|
/* if RA=0, the instruction form is invalid */
|
|
gen_invalid(ctx);
|
|
return true;
|
|
}
|
|
|
|
ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
|
|
helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);
|
|
return true;
|
|
}
|
|
|
|
TRANS(HASHST, do_hash, false, gen_helper_HASHST)
|
|
TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK)
|
|
TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP)
|
|
TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP)
|