e1b72c55b1
Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the
CPU type requested by the command line. This might confuse users,
since the following will create a machine with a Cortex-M4 CPU:
$ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f
Set the MachineClass::valid_cpu_types field (introduced in commit
c9cf636d48 "machine: Add a valid_cpu_types property").
Remove the now unused MachineClass::default_cpu_type field.
We now get:
$ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f
qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu
The valid types are: cortex-m4-arm-cpu
Since the SoC family can only use Cortex-M4 CPUs, hard-code the
CPU type name at the SoC level, removing the QOM property
entirely.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20231117071704.35040-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
/*
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* STM32F405 SoC
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_ARM_STM32F405_SOC_H
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#define HW_ARM_STM32F405_SOC_H
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#include "hw/misc/stm32f4xx_syscfg.h"
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#include "hw/timer/stm32f2xx_timer.h"
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#include "hw/char/stm32f2xx_usart.h"
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#include "hw/adc/stm32f2xx_adc.h"
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#include "hw/misc/stm32f4xx_exti.h"
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#include "hw/or-irq.h"
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#include "hw/ssi/stm32f2xx_spi.h"
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#include "hw/arm/armv7m.h"
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#include "qom/object.h"
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#define TYPE_STM32F405_SOC "stm32f405-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
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#define STM_NUM_USARTS 7
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#define STM_NUM_TIMERS 4
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#define STM_NUM_ADCS 6
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#define STM_NUM_SPIS 6
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#define FLASH_BASE_ADDRESS 0x08000000
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#define FLASH_SIZE (1024 * 1024)
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#define SRAM_BASE_ADDRESS 0x20000000
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#define SRAM_SIZE (128 * 1024)
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#define CCM_BASE_ADDRESS 0x10000000
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#define CCM_SIZE (64 * 1024)
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struct STM32F405State {
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SysBusDevice parent_obj;
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ARMv7MState armv7m;
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STM32F4xxSyscfgState syscfg;
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STM32F4xxExtiState exti;
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STM32F2XXUsartState usart[STM_NUM_USARTS];
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STM32F2XXTimerState timer[STM_NUM_TIMERS];
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OrIRQState adc_irqs;
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STM32F2XXADCState adc[STM_NUM_ADCS];
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STM32F2XXSPIState spi[STM_NUM_SPIS];
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MemoryRegion ccm;
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MemoryRegion sram;
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MemoryRegion flash;
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MemoryRegion flash_alias;
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Clock *sysclk;
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Clock *refclk;
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};
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#endif
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