1e0d985fa9
There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
933 lines
26 KiB
C
933 lines
26 KiB
C
/*
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* RISC-V Control and Status Registers.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "qemu/main-loop.h"
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#include "exec/exec-all.h"
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/* CSR function table */
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static riscv_csr_operations csr_ops[];
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/* CSR function table constants */
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enum {
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CSR_TABLE_SIZE = 0x1000
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};
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/* CSR function table public API */
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void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
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{
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*ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
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}
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void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
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{
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csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
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}
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/* Predicates */
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static int fs(CPURISCVState *env, int csrno)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
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return -1;
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}
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#endif
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return 0;
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}
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static int ctr(CPURISCVState *env, int csrno)
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{
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#if !defined(CONFIG_USER_ONLY)
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uint32_t ctr_en = ~0u;
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if (env->priv < PRV_M) {
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ctr_en &= env->mcounteren;
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}
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if (env->priv < PRV_S) {
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ctr_en &= env->scounteren;
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}
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if (!(ctr_en & (1u << (csrno & 31)))) {
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return -1;
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}
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#endif
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return 0;
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}
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#if !defined(CONFIG_USER_ONLY)
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static int any(CPURISCVState *env, int csrno)
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{
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return 0;
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}
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static int smode(CPURISCVState *env, int csrno)
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{
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return -!riscv_has_ext(env, RVS);
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}
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static int pmp(CPURISCVState *env, int csrno)
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{
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return -!riscv_feature(env, RISCV_FEATURE_PMP);
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}
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#endif
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/* User Floating-Point CSRs */
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static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
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return -1;
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}
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#endif
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*val = riscv_cpu_get_fflags(env);
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return 0;
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}
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static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
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return -1;
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}
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env->mstatus |= MSTATUS_FS;
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#endif
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riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
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return 0;
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}
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static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
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return -1;
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}
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#endif
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*val = env->frm;
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return 0;
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}
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static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
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return -1;
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}
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env->mstatus |= MSTATUS_FS;
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#endif
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env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
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return 0;
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}
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static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
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return -1;
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}
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#endif
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*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
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| (env->frm << FSR_RD_SHIFT);
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return 0;
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}
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static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
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return -1;
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}
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env->mstatus |= MSTATUS_FS;
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#endif
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env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
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riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
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return 0;
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}
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/* User Timers and Counters */
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static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (use_icount) {
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*val = cpu_get_icount();
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} else {
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*val = cpu_get_host_ticks();
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}
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#else
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*val = cpu_get_host_ticks();
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#endif
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return 0;
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}
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#if defined(TARGET_RISCV32)
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static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
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{
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#if !defined(CONFIG_USER_ONLY)
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if (use_icount) {
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*val = cpu_get_icount() >> 32;
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} else {
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*val = cpu_get_host_ticks() >> 32;
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}
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#else
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*val = cpu_get_host_ticks() >> 32;
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#endif
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return 0;
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}
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#endif /* TARGET_RISCV32 */
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#if defined(CONFIG_USER_ONLY)
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static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = cpu_get_host_ticks();
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return 0;
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}
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#if defined(TARGET_RISCV32)
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static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = cpu_get_host_ticks() >> 32;
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return 0;
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}
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#endif
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#else /* CONFIG_USER_ONLY */
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/* Machine constants */
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#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
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#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
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static const target_ulong delegable_ints = S_MODE_INTERRUPTS;
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static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS;
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static const target_ulong delegable_excps =
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(1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
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(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
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(1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
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(1ULL << (RISCV_EXCP_BREAKPOINT)) |
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(1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
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(1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
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(1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
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(1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
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(1ULL << (RISCV_EXCP_U_ECALL)) |
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(1ULL << (RISCV_EXCP_S_ECALL)) |
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(1ULL << (RISCV_EXCP_H_ECALL)) |
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(1ULL << (RISCV_EXCP_M_ECALL)) |
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(1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
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(1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
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(1ULL << (RISCV_EXCP_STORE_PAGE_FAULT));
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static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE |
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SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
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SSTATUS_SUM | SSTATUS_SD;
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static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
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SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
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SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
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static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
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#if defined(TARGET_RISCV32)
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static const char valid_vm_1_09[16] = {
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[VM_1_09_MBARE] = 1,
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[VM_1_09_SV32] = 1,
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};
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static const char valid_vm_1_10[16] = {
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[VM_1_10_MBARE] = 1,
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[VM_1_10_SV32] = 1
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};
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#elif defined(TARGET_RISCV64)
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static const char valid_vm_1_09[16] = {
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[VM_1_09_MBARE] = 1,
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[VM_1_09_SV39] = 1,
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[VM_1_09_SV48] = 1,
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};
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static const char valid_vm_1_10[16] = {
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[VM_1_10_MBARE] = 1,
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[VM_1_10_SV39] = 1,
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[VM_1_10_SV48] = 1,
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[VM_1_10_SV57] = 1
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};
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#endif /* CONFIG_USER_ONLY */
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/* Machine Information Registers */
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static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
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{
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return *val = 0;
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}
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static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->mhartid;
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return 0;
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}
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/* Machine Trap Setup */
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static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->mstatus;
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return 0;
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}
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static int validate_vm(CPURISCVState *env, target_ulong vm)
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{
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return (env->priv_ver >= PRIV_VERSION_1_10_0) ?
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valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf];
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}
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static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
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{
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target_ulong mstatus = env->mstatus;
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target_ulong mask = 0;
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/* flush tlb on mstatus fields that affect VM */
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if (env->priv_ver <= PRIV_VERSION_1_09_1) {
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if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
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MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
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tlb_flush(CPU(riscv_env_get_cpu(env)));
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}
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mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
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MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
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MSTATUS_MPP | MSTATUS_MXR |
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(validate_vm(env, get_field(val, MSTATUS_VM)) ?
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MSTATUS_VM : 0);
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}
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if (env->priv_ver >= PRIV_VERSION_1_10_0) {
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if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
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MSTATUS_MPRV | MSTATUS_SUM)) {
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tlb_flush(CPU(riscv_env_get_cpu(env)));
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}
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mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
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MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
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MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
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MSTATUS_TW;
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#if defined(TARGET_RISCV64)
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/*
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* RV32: MPV and MTL are not in mstatus. The current plan is to
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* add them to mstatush. For now, we just don't support it.
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*/
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mask |= MSTATUS_MPP | MSTATUS_MPV;
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#endif
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}
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mstatus = (mstatus & ~mask) | (val & mask);
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int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
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((mstatus & MSTATUS_XS) == MSTATUS_XS);
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mstatus = set_field(mstatus, MSTATUS_SD, dirty);
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env->mstatus = mstatus;
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return 0;
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}
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static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->misa;
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return 0;
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}
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static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
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{
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if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
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/* drop write to misa */
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return 0;
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}
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/* 'I' or 'E' must be present */
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if (!(val & (RVI | RVE))) {
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/* It is not, drop write to misa */
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return 0;
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}
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/* 'E' excludes all other extensions */
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if (val & RVE) {
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/* when we support 'E' we can do "val = RVE;" however
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* for now we just drop writes if 'E' is present.
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*/
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return 0;
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}
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/* Mask extensions that are not supported by this hart */
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val &= env->misa_mask;
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/* Mask extensions that are not supported by QEMU */
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val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
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if ((val & RVD) && !(val & RVF)) {
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val &= ~RVD;
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}
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/* Suppress 'C' if next instruction is not aligned
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* TODO: this should check next_pc
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*/
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if ((val & RVC) && (GETPC() & ~3) != 0) {
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val &= ~RVC;
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}
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/* misa.MXL writes are not supported by QEMU */
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val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
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/* flush translation cache */
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if (val != env->misa) {
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tb_flush(CPU(riscv_env_get_cpu(env)));
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}
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env->misa = val;
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return 0;
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}
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static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->medeleg;
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return 0;
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}
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static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
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{
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env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
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return 0;
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}
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static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->mideleg;
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return 0;
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}
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static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
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{
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env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
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return 0;
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}
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static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->mie;
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return 0;
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}
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static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
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{
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env->mie = (env->mie & ~all_ints) | (val & all_ints);
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return 0;
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}
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static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->mtvec;
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return 0;
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}
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static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
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{
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/* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
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if ((val & 3) < 2) {
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env->mtvec = val;
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} else {
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qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
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}
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return 0;
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}
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static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
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{
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if (env->priv_ver < PRIV_VERSION_1_10_0) {
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return -1;
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}
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*val = env->mcounteren;
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return 0;
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}
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static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
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{
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if (env->priv_ver < PRIV_VERSION_1_10_0) {
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return -1;
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}
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env->mcounteren = val;
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return 0;
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}
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static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
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{
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if (env->priv_ver > PRIV_VERSION_1_09_1) {
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return -1;
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}
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*val = env->mcounteren;
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return 0;
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}
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static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
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{
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if (env->priv_ver > PRIV_VERSION_1_09_1) {
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return -1;
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}
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env->mcounteren = val;
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return 0;
|
|
}
|
|
|
|
static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
if (env->priv_ver > PRIV_VERSION_1_09_1) {
|
|
return -1;
|
|
}
|
|
*val = env->scounteren;
|
|
return 0;
|
|
}
|
|
|
|
static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
if (env->priv_ver > PRIV_VERSION_1_09_1) {
|
|
return -1;
|
|
}
|
|
env->scounteren = val;
|
|
return 0;
|
|
}
|
|
|
|
/* Machine Trap Handling */
|
|
static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->mscratch;
|
|
return 0;
|
|
}
|
|
|
|
static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
env->mscratch = val;
|
|
return 0;
|
|
}
|
|
|
|
static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->mepc;
|
|
return 0;
|
|
}
|
|
|
|
static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
env->mepc = val;
|
|
return 0;
|
|
}
|
|
|
|
static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->mcause;
|
|
return 0;
|
|
}
|
|
|
|
static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
env->mcause = val;
|
|
return 0;
|
|
}
|
|
|
|
static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->mbadaddr;
|
|
return 0;
|
|
}
|
|
|
|
static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
env->mbadaddr = val;
|
|
return 0;
|
|
}
|
|
|
|
static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
|
|
target_ulong new_value, target_ulong write_mask)
|
|
{
|
|
RISCVCPU *cpu = riscv_env_get_cpu(env);
|
|
/* Allow software control of delegable interrupts not claimed by hardware */
|
|
target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
|
|
uint32_t old_mip;
|
|
|
|
if (mask) {
|
|
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
|
|
} else {
|
|
old_mip = atomic_read(&env->mip);
|
|
}
|
|
|
|
if (ret_value) {
|
|
*ret_value = old_mip;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Supervisor Trap Setup */
|
|
static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
|
|
sstatus_v1_10_mask : sstatus_v1_9_mask);
|
|
*val = env->mstatus & mask;
|
|
return 0;
|
|
}
|
|
|
|
static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
|
|
sstatus_v1_10_mask : sstatus_v1_9_mask);
|
|
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
|
|
return write_mstatus(env, CSR_MSTATUS, newval);
|
|
}
|
|
|
|
static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->mie & env->mideleg;
|
|
return 0;
|
|
}
|
|
|
|
static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg);
|
|
return write_mie(env, CSR_MIE, newval);
|
|
}
|
|
|
|
static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->stvec;
|
|
return 0;
|
|
}
|
|
|
|
static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
/* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
|
|
if ((val & 3) < 2) {
|
|
env->stvec = val;
|
|
} else {
|
|
qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
if (env->priv_ver < PRIV_VERSION_1_10_0) {
|
|
return -1;
|
|
}
|
|
*val = env->scounteren;
|
|
return 0;
|
|
}
|
|
|
|
static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
if (env->priv_ver < PRIV_VERSION_1_10_0) {
|
|
return -1;
|
|
}
|
|
env->scounteren = val;
|
|
return 0;
|
|
}
|
|
|
|
/* Supervisor Trap Handling */
|
|
static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->sscratch;
|
|
return 0;
|
|
}
|
|
|
|
static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
env->sscratch = val;
|
|
return 0;
|
|
}
|
|
|
|
static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->sepc;
|
|
return 0;
|
|
}
|
|
|
|
static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
env->sepc = val;
|
|
return 0;
|
|
}
|
|
|
|
static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->scause;
|
|
return 0;
|
|
}
|
|
|
|
static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
env->scause = val;
|
|
return 0;
|
|
}
|
|
|
|
static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = env->sbadaddr;
|
|
return 0;
|
|
}
|
|
|
|
static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
env->sbadaddr = val;
|
|
return 0;
|
|
}
|
|
|
|
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
|
|
target_ulong new_value, target_ulong write_mask)
|
|
{
|
|
int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
|
|
write_mask & env->mideleg & sip_writable_mask);
|
|
*ret_value &= env->mideleg;
|
|
return ret;
|
|
}
|
|
|
|
/* Supervisor Protection and Translation */
|
|
static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
|
|
*val = 0;
|
|
} else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
|
|
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
|
|
return -1;
|
|
} else {
|
|
*val = env->satp;
|
|
}
|
|
} else {
|
|
*val = env->sptbr;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
|
|
return 0;
|
|
}
|
|
if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) {
|
|
tlb_flush(CPU(riscv_env_get_cpu(env)));
|
|
env->sptbr = val & (((target_ulong)
|
|
1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
|
|
}
|
|
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
|
|
validate_vm(env, get_field(val, SATP_MODE)) &&
|
|
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
|
|
{
|
|
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
|
|
return -1;
|
|
} else {
|
|
if((val ^ env->satp) & SATP_ASID) {
|
|
tlb_flush(CPU(riscv_env_get_cpu(env)));
|
|
}
|
|
env->satp = val;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Physical Memory Protection */
|
|
static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
|
|
return 0;
|
|
}
|
|
|
|
static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
|
|
return 0;
|
|
}
|
|
|
|
static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
|
|
{
|
|
*val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
|
|
return 0;
|
|
}
|
|
|
|
static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
|
|
{
|
|
pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
* riscv_csrrw - read and/or update control and status register
|
|
*
|
|
* csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0);
|
|
* csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1);
|
|
* csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value);
|
|
* csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
|
|
*/
|
|
|
|
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
|
|
target_ulong new_value, target_ulong write_mask)
|
|
{
|
|
int ret;
|
|
target_ulong old_value;
|
|
|
|
/* check privileges and return -1 if check fails */
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
int csr_priv = get_field(csrno, 0x300);
|
|
int read_only = get_field(csrno, 0xC00) == 3;
|
|
if ((write_mask && read_only) || (env->priv < csr_priv)) {
|
|
return -1;
|
|
}
|
|
#endif
|
|
|
|
/* check predicate */
|
|
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
|
|
return -1;
|
|
}
|
|
|
|
/* execute combined read/write operation if it exists */
|
|
if (csr_ops[csrno].op) {
|
|
return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
|
|
}
|
|
|
|
/* if no accessor exists then return failure */
|
|
if (!csr_ops[csrno].read) {
|
|
return -1;
|
|
}
|
|
|
|
/* read old value */
|
|
ret = csr_ops[csrno].read(env, csrno, &old_value);
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
/* write value if writable and write mask set, otherwise drop writes */
|
|
if (write_mask) {
|
|
new_value = (old_value & ~write_mask) | (new_value & write_mask);
|
|
if (csr_ops[csrno].write) {
|
|
ret = csr_ops[csrno].write(env, csrno, new_value);
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* return old value */
|
|
if (ret_value) {
|
|
*ret_value = old_value;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Debugger support. If not in user mode, set env->debugger before the
|
|
* riscv_csrrw call and clear it after the call.
|
|
*/
|
|
int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
|
|
target_ulong new_value, target_ulong write_mask)
|
|
{
|
|
int ret;
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
env->debugger = true;
|
|
#endif
|
|
ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
env->debugger = false;
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
/* Control and Status Register function table */
|
|
static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
|
|
/* User Floating-Point CSRs */
|
|
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
|
|
[CSR_FRM] = { fs, read_frm, write_frm },
|
|
[CSR_FCSR] = { fs, read_fcsr, write_fcsr },
|
|
|
|
/* User Timers and Counters */
|
|
[CSR_CYCLE] = { ctr, read_instret },
|
|
[CSR_INSTRET] = { ctr, read_instret },
|
|
#if defined(TARGET_RISCV32)
|
|
[CSR_CYCLEH] = { ctr, read_instreth },
|
|
[CSR_INSTRETH] = { ctr, read_instreth },
|
|
#endif
|
|
|
|
/* User-level time CSRs are only available in linux-user
|
|
* In privileged mode, the monitor emulates these CSRs */
|
|
#if defined(CONFIG_USER_ONLY)
|
|
[CSR_TIME] = { ctr, read_time },
|
|
#if defined(TARGET_RISCV32)
|
|
[CSR_TIMEH] = { ctr, read_timeh },
|
|
#endif
|
|
#endif
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
/* Machine Timers and Counters */
|
|
[CSR_MCYCLE] = { any, read_instret },
|
|
[CSR_MINSTRET] = { any, read_instret },
|
|
#if defined(TARGET_RISCV32)
|
|
[CSR_MCYCLEH] = { any, read_instreth },
|
|
[CSR_MINSTRETH] = { any, read_instreth },
|
|
#endif
|
|
|
|
/* Machine Information Registers */
|
|
[CSR_MVENDORID] = { any, read_zero },
|
|
[CSR_MARCHID] = { any, read_zero },
|
|
[CSR_MIMPID] = { any, read_zero },
|
|
[CSR_MHARTID] = { any, read_mhartid },
|
|
|
|
/* Machine Trap Setup */
|
|
[CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
|
|
[CSR_MISA] = { any, read_misa, write_misa },
|
|
[CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
|
|
[CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
|
|
[CSR_MIE] = { any, read_mie, write_mie },
|
|
[CSR_MTVEC] = { any, read_mtvec, write_mtvec },
|
|
[CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
|
|
|
|
/* Legacy Counter Setup (priv v1.9.1) */
|
|
[CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren },
|
|
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
|
|
|
|
/* Machine Trap Handling */
|
|
[CSR_MSCRATCH] = { any, read_mscratch, write_mscratch },
|
|
[CSR_MEPC] = { any, read_mepc, write_mepc },
|
|
[CSR_MCAUSE] = { any, read_mcause, write_mcause },
|
|
[CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr },
|
|
[CSR_MIP] = { any, NULL, NULL, rmw_mip },
|
|
|
|
/* Supervisor Trap Setup */
|
|
[CSR_SSTATUS] = { smode, read_sstatus, write_sstatus },
|
|
[CSR_SIE] = { smode, read_sie, write_sie },
|
|
[CSR_STVEC] = { smode, read_stvec, write_stvec },
|
|
[CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren },
|
|
|
|
/* Supervisor Trap Handling */
|
|
[CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch },
|
|
[CSR_SEPC] = { smode, read_sepc, write_sepc },
|
|
[CSR_SCAUSE] = { smode, read_scause, write_scause },
|
|
[CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr },
|
|
[CSR_SIP] = { smode, NULL, NULL, rmw_sip },
|
|
|
|
/* Supervisor Protection and Translation */
|
|
[CSR_SATP] = { smode, read_satp, write_satp },
|
|
|
|
/* Physical Memory Protection */
|
|
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
|
|
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
|
|
|
|
/* Performance Counters */
|
|
[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
|
|
[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
|
|
[CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
|
|
#if defined(TARGET_RISCV32)
|
|
[CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero },
|
|
[CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero },
|
|
#endif
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
};
|