qemu/target-openrisc
Benjamin Herrenschmidt 97ed5ccdee tlb: Add "ifetch" argument to cpu_mmu_index()
This is set to true when the index is for an instruction fetch
translation.

The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS
acessors.

All targets ignore it for now, and all other callers pass "false".

This will allow targets who wish to split the mmu index between
instruction and data accesses to do so. A subsequent patch will
do just that for PowerPC.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11 08:15:28 -07:00
..
cpu.c cpu: Change cpu_exec_init() arg to cpu, not env 2015-07-09 15:20:40 +02:00
cpu.h tlb: Add "ifetch" argument to cpu_mmu_index() 2015-09-11 08:15:28 -07:00
exception_helper.c tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
exception.c cpu-exec: Change cpu_loop_exit() argument to CPUState 2014-03-13 19:20:47 +01:00
exception.h
fpu_helper.c tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
helper.h tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
int_helper.c tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
interrupt_helper.c tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
interrupt.c target-openrisc: Use cpu_exec_interrupt qom hook 2014-09-25 18:54:22 +01:00
machine.c savevm: Remove all the unneeded version_minimum_id_old (rest) 2014-05-14 15:24:51 +02:00
Makefile.objs cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
mmu_helper.c softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
mmu.c cputlb: Change tlb_set_page() argument to CPUState 2014-03-13 19:52:47 +01:00
sys_helper.c tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
translate.c tlb: Add "ifetch" argument to cpu_mmu_index() 2015-09-11 08:15:28 -07:00