30efbf330a
QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
13 lines
440 B
Makefile
13 lines
440 B
Makefile
obj-$(CONFIG_SPIKE) += riscv_htif.o
|
|
obj-$(CONFIG_HART) += riscv_hart.o
|
|
obj-$(CONFIG_SIFIVE_E) += sifive_e.o
|
|
obj-$(CONFIG_SIFIVE) += sifive_clint.o
|
|
obj-$(CONFIG_SIFIVE) += sifive_gpio.o
|
|
obj-$(CONFIG_SIFIVE) += sifive_prci.o
|
|
obj-$(CONFIG_SIFIVE) += sifive_plic.o
|
|
obj-$(CONFIG_SIFIVE) += sifive_test.o
|
|
obj-$(CONFIG_SIFIVE_U) += sifive_u.o
|
|
obj-$(CONFIG_SIFIVE) += sifive_uart.o
|
|
obj-$(CONFIG_SPIKE) += spike.o
|
|
obj-$(CONFIG_RISCV_VIRT) += virt.o
|