Tsukasa OI 4bcfc391ac hw/riscv: Make CPU config error handling generous (virt/spike) ...

If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system).  This kind of error handling should be used only when a serious
runtime error occurs.

This commit makes error handling on CPU configuration more generous on
virt/spike machines.  It now just prints error message and quits (without
coredumps and aborts).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-05-24 10:38:50 +10:00

..

boot.c

hw/riscv: boot: Support 64bit fdt address.

2022-04-22 10:35:16 +10:00

Kconfig

hw/riscv: Enable TPM backends

2022-04-29 10:48:48 +10:00

meson.build

…

microchip_pfsoc.c

hw/riscv: Don't add empty bootargs to device tree

2022-04-29 10:47:45 +10:00

numa.c

…

opentitan.c

…

riscv_hart.c

…

shakti_c.c

…

sifive_e.c

…

sifive_u.c

hw/riscv: Don't add empty bootargs to device tree

2022-04-29 10:47:45 +10:00

spike.c

hw/riscv: Make CPU config error handling generous (virt/spike)

2022-05-24 10:38:50 +10:00

virt.c

hw/riscv: Make CPU config error handling generous (virt/spike)

2022-05-24 10:38:50 +10:00