8c71baedb8
Move some stuff that will be common to both translate-a64.c and translate-sve.c. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
119 lines
4.5 KiB
C
119 lines
4.5 KiB
C
/*
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* AArch64 translation, common definitions.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TARGET_ARM_TRANSLATE_A64_H
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#define TARGET_ARM_TRANSLATE_A64_H
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void unallocated_encoding(DisasContext *s);
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#define unsupported_encoding(s, insn) \
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do { \
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qemu_log_mask(LOG_UNIMP, \
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"%s:%d: unsupported instruction encoding 0x%08x " \
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"at pc=%016" PRIx64 "\n", \
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__FILE__, __LINE__, insn, s->pc - 4); \
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unallocated_encoding(s); \
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} while (0)
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TCGv_i64 new_tmp_a64(DisasContext *s);
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TCGv_i64 new_tmp_a64_zero(DisasContext *s);
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TCGv_i64 cpu_reg(DisasContext *s, int reg);
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TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
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TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
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TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);
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void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
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TCGv_ptr get_fpstatus_ptr(bool);
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bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
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unsigned int imms, unsigned int immr);
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uint64_t vfp_expand_imm(int size, uint8_t imm8);
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bool sve_access_check(DisasContext *s);
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/* We should have at some point before trying to access an FP register
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* done the necessary access check, so assert that
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* (a) we did the check and
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* (b) we didn't then just plough ahead anyway if it failed.
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* Print the instruction pattern in the abort message so we can figure
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* out what we need to fix if a user encounters this problem in the wild.
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*/
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static inline void assert_fp_access_checked(DisasContext *s)
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{
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#ifdef CONFIG_DEBUG_TCG
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if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
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fprintf(stderr, "target-arm: FP access check missing for "
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"instruction 0x%08x\n", s->insn);
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abort();
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}
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#endif
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}
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/* Return the offset into CPUARMState of an element of specified
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* size, 'element' places in from the least significant end of
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* the FP/vector register Qn.
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*/
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static inline int vec_reg_offset(DisasContext *s, int regno,
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int element, TCGMemOp size)
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{
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int offs = 0;
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#ifdef HOST_WORDS_BIGENDIAN
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/* This is complicated slightly because vfp.zregs[n].d[0] is
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* still the low half and vfp.zregs[n].d[1] the high half
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* of the 128 bit vector, even on big endian systems.
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* Calculate the offset assuming a fully bigendian 128 bits,
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* then XOR to account for the order of the two 64 bit halves.
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*/
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offs += (16 - ((element + 1) * (1 << size)));
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offs ^= 8;
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#else
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offs += element * (1 << size);
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#endif
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offs += offsetof(CPUARMState, vfp.zregs[regno]);
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assert_fp_access_checked(s);
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return offs;
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}
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/* Return the offset info CPUARMState of the "whole" vector register Qn. */
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static inline int vec_full_reg_offset(DisasContext *s, int regno)
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{
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assert_fp_access_checked(s);
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return offsetof(CPUARMState, vfp.zregs[regno]);
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}
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/* Return a newly allocated pointer to the vector register. */
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static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
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{
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TCGv_ptr ret = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
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return ret;
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}
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/* Return the byte size of the "whole" vector register, VL / 8. */
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static inline int vec_full_reg_size(DisasContext *s)
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{
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return s->sve_len;
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}
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bool disas_sve(DisasContext *, uint32_t);
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/* Note that the gvec expanders operate on offsets + sizes. */
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typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
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typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
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uint32_t, uint32_t);
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typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
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uint32_t, uint32_t, uint32_t);
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#endif /* TARGET_ARM_TRANSLATE_A64_H */
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