e34f86a2f9
The values in env->flags are a subset of tb->flags. Restore only the bits that belong. Cc: qemu-stable@nongnu.org Fixes:ab419fd8a0
("target/sh4: Fix TB_FLAG_UNALIGN") Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-ID: <20221212011345.GA2235238@roeck-us.net> [rth: Reduce to only the the superh_cpu_synchronize_from_tb change] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> (cherry picked from commitbc2331635c
) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
327 lines
9.0 KiB
C
327 lines
9.0 KiB
C
/*
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* QEMU SuperH CPU
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*
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* Copyright (c) 2005 Samuel Tardieu
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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#include "migration/vmstate.h"
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#include "exec/exec-all.h"
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#include "fpu/softfloat-helpers.h"
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static void superh_cpu_set_pc(CPUState *cs, vaddr value)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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cpu->env.pc = value;
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}
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static vaddr superh_cpu_get_pc(CPUState *cs)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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return cpu->env.pc;
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}
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static void superh_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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cpu->env.pc = tb_pc(tb);
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cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
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}
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static void superh_restore_state_to_opc(CPUState *cs,
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const TranslationBlock *tb,
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const uint64_t *data)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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cpu->env.pc = data[0];
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cpu->env.flags = data[1];
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/*
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* Theoretically delayed_pc should also be restored. In practice the
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* branch instruction is re-executed after exception, so the delayed
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* branch target will be recomputed.
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*/
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}
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#ifndef CONFIG_USER_ONLY
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static bool superh_io_recompile_replay_branch(CPUState *cs,
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const TranslationBlock *tb)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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CPUSH4State *env = &cpu->env;
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if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
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&& env->pc != tb_pc(tb)) {
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env->pc -= 2;
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env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
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return true;
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}
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return false;
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}
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#endif
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static bool superh_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & CPU_INTERRUPT_HARD;
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}
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static void superh_cpu_reset(DeviceState *dev)
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{
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CPUState *s = CPU(dev);
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SuperHCPU *cpu = SUPERH_CPU(s);
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
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CPUSH4State *env = &cpu->env;
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scc->parent_reset(dev);
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memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
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env->pc = 0xA0000000;
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#if defined(CONFIG_USER_ONLY)
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env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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#else
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env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
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(1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
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env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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#endif
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set_default_nan_mode(1, &env->fp_status);
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}
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static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_mach_sh4;
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info->print_insn = print_insn_sh;
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}
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static void superh_cpu_list_entry(gpointer data, gpointer user_data)
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{
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const char *typename = object_class_get_name(OBJECT_CLASS(data));
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int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX);
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qemu_printf("%.*s\n", len, typename);
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}
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void sh4_cpu_list(void)
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{
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GSList *list;
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list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false);
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g_slist_foreach(list, superh_cpu_list_entry, NULL);
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g_slist_free(list);
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}
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static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *s, *typename = NULL;
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s = g_ascii_strdown(cpu_model, -1);
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if (strcmp(s, "any") == 0) {
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oc = object_class_by_name(TYPE_SH7750R_CPU);
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goto out;
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}
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typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
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oc = object_class_by_name(typename);
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if (oc != NULL && object_class_is_abstract(oc)) {
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oc = NULL;
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}
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out:
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g_free(s);
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g_free(typename);
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return oc;
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}
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static void sh7750r_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7750R;
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env->features = SH_FEATURE_BCR3_AND_BCR4;
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}
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static void sh7750r_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->pvr = 0x00050000;
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scc->prr = 0x00000100;
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scc->cvr = 0x00110000;
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}
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static void sh7751r_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7751R;
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env->features = SH_FEATURE_BCR3_AND_BCR4;
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}
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static void sh7751r_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->pvr = 0x04050005;
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scc->prr = 0x00000113;
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scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
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}
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static void sh7785_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7785;
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env->features = SH_FEATURE_SH4A;
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}
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static void sh7785_class_init(ObjectClass *oc, void *data)
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{
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->pvr = 0x10300700;
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scc->prr = 0x00000200;
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scc->cvr = 0x71440211;
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}
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static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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scc->parent_realize(dev, errp);
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}
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static void superh_cpu_initfn(Object *obj)
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{
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SuperHCPU *cpu = SUPERH_CPU(obj);
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CPUSH4State *env = &cpu->env;
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cpu_set_cpustate_pointers(cpu);
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env->movcal_backup_tail = &(env->movcal_backup);
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}
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#ifndef CONFIG_USER_ONLY
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static const VMStateDescription vmstate_sh_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps sh4_sysemu_ops = {
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.get_phys_page_debug = superh_cpu_get_phys_page_debug,
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};
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#endif
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#include "hw/core/tcg-cpu-ops.h"
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static const struct TCGCPUOps superh_tcg_ops = {
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.initialize = sh4_translate_init,
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.synchronize_from_tb = superh_cpu_synchronize_from_tb,
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.restore_state_to_opc = superh_restore_state_to_opc,
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#ifndef CONFIG_USER_ONLY
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.tlb_fill = superh_cpu_tlb_fill,
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.cpu_exec_interrupt = superh_cpu_exec_interrupt,
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.do_interrupt = superh_cpu_do_interrupt,
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.do_unaligned_access = superh_cpu_do_unaligned_access,
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.io_recompile_replay_branch = superh_io_recompile_replay_branch,
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#endif /* !CONFIG_USER_ONLY */
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};
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static void superh_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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device_class_set_parent_realize(dc, superh_cpu_realizefn,
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&scc->parent_realize);
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device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset);
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cc->class_by_name = superh_cpu_class_by_name;
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cc->has_work = superh_cpu_has_work;
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cc->dump_state = superh_cpu_dump_state;
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cc->set_pc = superh_cpu_set_pc;
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cc->get_pc = superh_cpu_get_pc;
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cc->gdb_read_register = superh_cpu_gdb_read_register;
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cc->gdb_write_register = superh_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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cc->sysemu_ops = &sh4_sysemu_ops;
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dc->vmsd = &vmstate_sh_cpu;
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#endif
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cc->disas_set_info = superh_cpu_disas_set_info;
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cc->gdb_num_core_regs = 59;
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cc->tcg_ops = &superh_tcg_ops;
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}
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#define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
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{ \
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.name = type_name, \
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.parent = TYPE_SUPERH_CPU, \
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.class_init = cinit, \
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.instance_init = initfn, \
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}
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static const TypeInfo superh_cpu_type_infos[] = {
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{
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.name = TYPE_SUPERH_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(SuperHCPU),
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.instance_init = superh_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(SuperHCPUClass),
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.class_init = superh_cpu_class_init,
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},
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DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
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sh7750r_cpu_initfn),
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DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
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sh7751r_cpu_initfn),
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DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
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sh7785_cpu_initfn),
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};
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DEFINE_TYPES(superh_cpu_type_infos)
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