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Stefan Hajnoczi 4a9c04672a Cache CPUClass for use in hot code paths. 
Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
 Add generic support for TARGET_TB_PCREL.
 tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
 target/sh4: Fix TB_FLAG_UNALIGN
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Merge tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu into staging

Cache CPUClass for use in hot code paths.
Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
Add generic support for TARGET_TB_PCREL.
tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
target/sh4: Fix TB_FLAG_UNALIGN

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* tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu:
  target/sh4: Fix TB_FLAG_UNALIGN
  tcg/ppc: Optimize 26-bit jumps
  accel/tcg: Introduce TARGET_TB_PCREL
  accel/tcg: Introduce tb_pc and log_pc
  hw/core: Add CPUClass.get_pc
  include/hw/core: Create struct CPUJumpCache
  accel/tcg: Inline tb_flush_jmp_cache
  accel/tcg: Do not align tb->page_addr[0]
  accel/tcg: Use DisasContextBase in plugin_gen_tb_start
  accel/tcg: Use bool for page_find_alloc
  accel/tcg: Remove PageDesc code_bitmap
  include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
  accel/tcg: Introduce tlb_set_page_full
  accel/tcg: Introduce probe_access_full
  accel/tcg: Suppress auto-invalidate in probe_access_internal
  accel/tcg: Drop addr member from SavedIOTLB
  accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
  cputlb: used cached CPUClass in our hot-paths
  hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
  cpu: cache CPUClass in CPUState for hot code paths

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-10-05 10:17:02 -04:00
..
alpha hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
arm accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
avr accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
cris hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
hexagon accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
hppa accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
i386 Cache CPUClass for use in hot code paths. 2022-10-05 10:17:02 -04:00
loongarch accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
m68k hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
microblaze accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
mips accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
nios2 hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
openrisc accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
ppc hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
riscv accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
rx accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
s390x hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
sh4 target/sh4: Fix TB_FLAG_UNALIGN 2022-10-04 12:33:05 -07:00
sparc accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
tricore accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
xtensa hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00