ea84a44250
The guest OS reads RSTAT, RSEQ, and RINTR, and expects those registers to reflect a consistent state. However, it is possible that the registers can change after RSTAT was read, but before RINTR is read, when esp_command_complete() is called. Guest OS qemu -------- ---- [handle interrupt] Read RSTAT esp_command_complete() RSTAT = STAT_ST esp_dma_done() RSTAT |= STAT_TC RSEQ = 0 RINTR = INTR_BS Read RSEQ Read RINTR RINTR = 0 RSTAT &= ~STAT_TC RSEQ = SEQ_CD The guest OS would then try to handle INTR_BS combined with an old value of RSTAT. This sometimes resulted in lost events, spurious interrupts, guest OS confusion, and stalled SCSI operations. A typical guest error log (observed with various versions of Linux) looks as follows. scsi host1: Spurious irq, sreg=13. ... scsi host1: Aborting command [84531f10:2a] scsi host1: Current command [f882eea8:35] scsi host1: Queued command [84531f10:2a] scsi host1: Active command [f882eea8:35] scsi host1: Dumping command log scsi host1: ent[15] CMD val[44] sreg[90] seqreg[00] sreg2[00] ireg[20] ss[00] event[0c] scsi host1: ent[16] CMD val[01] sreg[90] seqreg[00] sreg2[00] ireg[20] ss[02] event[0c] scsi host1: ent[17] CMD val[43] sreg[90] seqreg[00] sreg2[00] ireg[20] ss[02] event[0c] scsi host1: ent[18] EVENT val[0d] sreg[92] seqreg[04] sreg2[00] ireg[18] ss[00] event[0c] ... Defer handling command completion until previous interrupts have been handled to fix the problem. Signed-off-by: Guenter Roeck <linux@roeck-us.net>
146 lines
3.2 KiB
C
146 lines
3.2 KiB
C
#ifndef QEMU_HW_ESP_H
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#define QEMU_HW_ESP_H
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#include "hw/scsi/scsi.h"
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#include "hw/sysbus.h"
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/* esp.c */
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#define ESP_MAX_DEVS 7
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typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
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#define ESP_REGS 16
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#define TI_BUFSZ 16
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#define ESP_CMDBUF_SZ 32
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typedef struct ESPState ESPState;
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struct ESPState {
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uint8_t rregs[ESP_REGS];
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uint8_t wregs[ESP_REGS];
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qemu_irq irq;
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uint8_t chip_id;
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bool tchi_written;
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int32_t ti_size;
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uint32_t ti_rptr, ti_wptr;
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uint32_t status;
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uint32_t deferred_status;
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bool deferred_complete;
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uint32_t dma;
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uint8_t ti_buf[TI_BUFSZ];
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SCSIBus bus;
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SCSIDevice *current_dev;
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SCSIRequest *current_req;
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uint8_t cmdbuf[ESP_CMDBUF_SZ];
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uint32_t cmdlen;
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uint32_t do_cmd;
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/* The amount of data left in the current DMA transfer. */
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uint32_t dma_left;
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/* The size of the current DMA transfer. Zero if no transfer is in
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progress. */
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uint32_t dma_counter;
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int dma_enabled;
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uint32_t async_len;
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uint8_t *async_buf;
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ESPDMAMemoryReadWriteFunc dma_memory_read;
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ESPDMAMemoryReadWriteFunc dma_memory_write;
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void *dma_opaque;
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void (*dma_cb)(ESPState *s);
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};
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#define TYPE_ESP "esp"
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#define ESP_STATE(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
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typedef struct {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t it_shift;
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ESPState esp;
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} SysBusESPState;
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#define ESP_TCLO 0x0
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#define ESP_TCMID 0x1
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#define ESP_FIFO 0x2
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#define ESP_CMD 0x3
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#define ESP_RSTAT 0x4
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#define ESP_WBUSID 0x4
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#define ESP_RINTR 0x5
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#define ESP_WSEL 0x5
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#define ESP_RSEQ 0x6
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#define ESP_WSYNTP 0x6
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#define ESP_RFLAGS 0x7
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#define ESP_WSYNO 0x7
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#define ESP_CFG1 0x8
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#define ESP_RRES1 0x9
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#define ESP_WCCF 0x9
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#define ESP_RRES2 0xa
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#define ESP_WTEST 0xa
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#define ESP_CFG2 0xb
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#define ESP_CFG3 0xc
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#define ESP_RES3 0xd
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#define ESP_TCHI 0xe
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#define ESP_RES4 0xf
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#define CMD_DMA 0x80
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#define CMD_CMD 0x7f
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#define CMD_NOP 0x00
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#define CMD_FLUSH 0x01
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#define CMD_RESET 0x02
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#define CMD_BUSRESET 0x03
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#define CMD_TI 0x10
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#define CMD_ICCS 0x11
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#define CMD_MSGACC 0x12
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#define CMD_PAD 0x18
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#define CMD_SATN 0x1a
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#define CMD_RSTATN 0x1b
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#define CMD_SEL 0x41
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#define CMD_SELATN 0x42
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#define CMD_SELATNS 0x43
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#define CMD_ENSEL 0x44
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#define CMD_DISSEL 0x45
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#define STAT_DO 0x00
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#define STAT_DI 0x01
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#define STAT_CD 0x02
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#define STAT_ST 0x03
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#define STAT_MO 0x06
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#define STAT_MI 0x07
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#define STAT_PIO_MASK 0x06
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#define STAT_TC 0x10
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#define STAT_PE 0x20
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#define STAT_GE 0x40
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#define STAT_INT 0x80
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#define BUSID_DID 0x07
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#define INTR_FC 0x08
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#define INTR_BS 0x10
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#define INTR_DC 0x20
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#define INTR_RST 0x80
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#define SEQ_0 0x0
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#define SEQ_CD 0x4
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#define CFG1_RESREPT 0x40
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#define TCHI_FAS100A 0x4
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#define TCHI_AM53C974 0x12
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void esp_dma_enable(ESPState *s, int irq, int level);
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void esp_request_cancelled(SCSIRequest *req);
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void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
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void esp_transfer_data(SCSIRequest *req, uint32_t len);
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void esp_hard_reset(ESPState *s);
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uint64_t esp_reg_read(ESPState *s, uint32_t saddr);
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void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val);
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extern const VMStateDescription vmstate_esp;
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#endif
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