4c7f4f4f05
RISC-V also needs to use the same code to create fw_cfg in DSDT. So, avoid code duplication by moving the code in arm and riscv to a device specific file. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-2-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21 lines
1.3 KiB
Meson
21 lines
1.3 KiB
Meson
system_ss.add(files('fw_cfg-interface.c'))
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system_ss.add(files('fw_cfg.c'))
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system_ss.add(when: 'CONFIG_CHRP_NVRAM', if_true: files('chrp_nvram.c'))
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system_ss.add(when: 'CONFIG_DS1225Y', if_true: files('ds1225y.c'))
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system_ss.add(when: 'CONFIG_NMC93XX_EEPROM', if_true: files('eeprom93xx.c'))
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system_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
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system_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
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system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
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system_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
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system_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
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system_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
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system_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
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'xlnx-versal-efuse-cache.c',
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'xlnx-versal-efuse-ctrl.c'))
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system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
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'xlnx-zynqmp-efuse.c'))
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system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
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specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
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specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
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