qemu/include/hw/i386
Radim Krčmář 5232d00a04 target-i386: Implement CPUID[0xB] (Extended Topology Enumeration)
I looked at a dozen Intel CPU that have this CPUID and all of them
always had Core offset as 1 (a wasted bit when hyperthreading is
disabled) and Package offset at least 4 (wasted bits at <= 4 cores).

QEMU uses more compact IDs and it doesn't make much sense to change it
now.  I keep the SMT and Core sub-leaves even if there is just one
thread/core;  it makes the code simpler and there should be no harm.

Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-06-14 16:17:08 -03:00
..
apic_internal.h cpu/apic: drop icc bus/bridge 2015-10-02 16:22:02 -03:00
apic-msidef.h
apic.h apic: move target-dependent definitions to cpu.h 2016-05-19 16:42:28 +02:00
ich9.h ICH9: fix typo 2016-06-07 18:19:23 +03:00
intel_iommu.h intel_iommu: large page support 2016-02-06 20:44:10 +02:00
ioapic_internal.h ioapic: keep RO bits for IOAPIC entry 2016-05-23 16:53:43 +02:00
ioapic.h pc: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/ioapic.h 2013-07-29 19:33:32 -05:00
pc.h target-i386: Implement CPUID[0xB] (Extended Topology Enumeration) 2016-06-14 16:17:08 -03:00
topology.h include: Clean up includes 2016-02-23 12:43:05 +00:00