0411a97258
routines. Coming back to a raw MSR storage model then speed-up the emulation. Improve fast MSR updates (wrtee wrteei and mtriee cases). Share rfi family instructions helpers code to avoid bug in duplicated code. Allow entering halt mode as the result of a rfi instruction. Add a new helper_regs.h file to avoid duplication of special registers manipulation routines (currently XER and MSR). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3436 c046a42c-6fe2-441c-8c8c-71466251a162
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
/*
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* PowerPC emulation definitions for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !defined (__PPC_H__)
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#define __PPC_H__
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#include "config.h"
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#include "dyngen-exec.h"
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#include "cpu.h"
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#include "exec-all.h"
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/* For normal operations, precise emulation should not be needed */
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//#define USE_PRECISE_EMULATION 1
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#define USE_PRECISE_EMULATION 0
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register struct CPUPPCState *env asm(AREG0);
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* no registers can be used */
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#define T0 (env->t0)
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#define T1 (env->t1)
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#define T2 (env->t2)
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#else
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register unsigned long T0 asm(AREG1);
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register unsigned long T1 asm(AREG2);
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register unsigned long T2 asm(AREG3);
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#endif
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/* We may, sometime, need 64 bits registers on 32 bits target */
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#if TARGET_GPR_BITS > HOST_LONG_BITS
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/* no registers can be used */
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#define T0_64 (env->t0)
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#define T1_64 (env->t1)
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#define T2_64 (env->t2)
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#else
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#define T0_64 T0
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#define T1_64 T1
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#define T2_64 T2
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#endif
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/* Provision for Altivec */
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#define AVR0 (env->avr0)
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#define AVR1 (env->avr1)
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#define AVR2 (env->avr2)
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#define FT0 (env->ft0)
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#define FT1 (env->ft1)
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#define FT2 (env->ft2)
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#if defined (DEBUG_OP)
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# define RETURN() __asm__ __volatile__("nop" : : : "memory");
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#else
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# define RETURN() __asm__ __volatile__("" : : : "memory");
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#endif
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static always_inline target_ulong rotl8 (target_ulong i, int n)
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{
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return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n)));
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}
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static always_inline target_ulong rotl16 (target_ulong i, int n)
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{
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return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n)));
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}
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static always_inline target_ulong rotl32 (target_ulong i, int n)
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{
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return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n)));
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}
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#if defined(TARGET_PPC64)
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static always_inline target_ulong rotl64 (target_ulong i, int n)
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{
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return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n)));
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h"
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#endif /* !defined(CONFIG_USER_ONLY) */
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void do_raise_exception_err (uint32_t exception, int error_code);
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void do_raise_exception (uint32_t exception);
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int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
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int rw, int access_type, int check_BATs);
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void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
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target_ulong pte0, target_ulong pte1);
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static always_inline void env_to_regs (void)
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{
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}
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static always_inline void regs_to_env (void)
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{
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}
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int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu);
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static always_inline int cpu_halted (CPUState *env)
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{
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if (!env->halted)
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return 0;
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if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
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env->halted = 0;
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return 0;
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}
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return EXCP_HALTED;
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}
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#endif /* !defined (__PPC_H__) */
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