49afbca3b0
Now that we have separated the gl and non-gl code flows to two different devices there is little reason turn on and off virglrenderer usage at runtime. The gl code can simply use virglrenderer unconditionally. So drop use_virgl_renderer field and just do that. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20210430113547.1816178-1-kraxel@redhat.com Message-Id: <20210430113547.1816178-13-kraxel@redhat.com>
249 lines
7.7 KiB
C
249 lines
7.7 KiB
C
/*
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* Virtio GPU Device
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*
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* Copyright Red Hat, Inc. 2013-2014
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*
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* Authors:
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* Dave Airlie <airlied@redhat.com>
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* Gerd Hoffmann <kraxel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef HW_VIRTIO_GPU_H
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#define HW_VIRTIO_GPU_H
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#include "qemu/queue.h"
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#include "ui/qemu-pixman.h"
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#include "ui/console.h"
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#include "hw/virtio/virtio.h"
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#include "qemu/log.h"
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#include "sysemu/vhost-user-backend.h"
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#include "standard-headers/linux/virtio_gpu.h"
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#include "qom/object.h"
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#define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
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OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass,
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VIRTIO_GPU_BASE)
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#define TYPE_VIRTIO_GPU "virtio-gpu-device"
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OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU)
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#define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device"
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OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL)
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#define TYPE_VHOST_USER_GPU "vhost-user-gpu"
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OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU)
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#define VIRTIO_ID_GPU 16
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struct virtio_gpu_simple_resource {
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uint32_t resource_id;
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uint32_t width;
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uint32_t height;
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uint32_t format;
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uint64_t *addrs;
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struct iovec *iov;
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unsigned int iov_cnt;
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uint32_t scanout_bitmask;
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pixman_image_t *image;
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uint64_t hostmem;
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QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
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};
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struct virtio_gpu_scanout {
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QemuConsole *con;
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DisplaySurface *ds;
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uint32_t width, height;
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int x, y;
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int invalidate;
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uint32_t resource_id;
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struct virtio_gpu_update_cursor cursor;
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QEMUCursor *current_cursor;
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};
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struct virtio_gpu_requested_state {
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uint16_t width_mm, height_mm;
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uint32_t width, height;
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int x, y;
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};
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enum virtio_gpu_base_conf_flags {
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VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
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VIRTIO_GPU_FLAG_STATS_ENABLED,
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VIRTIO_GPU_FLAG_EDID_ENABLED,
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VIRTIO_GPU_FLAG_DMABUF_ENABLED,
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};
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#define virtio_gpu_virgl_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
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#define virtio_gpu_stats_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
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#define virtio_gpu_edid_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
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#define virtio_gpu_dmabuf_enabled(_cfg) \
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(_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED))
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struct virtio_gpu_base_conf {
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uint32_t max_outputs;
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uint32_t flags;
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uint32_t xres;
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uint32_t yres;
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};
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struct virtio_gpu_ctrl_command {
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VirtQueueElement elem;
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VirtQueue *vq;
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struct virtio_gpu_ctrl_hdr cmd_hdr;
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uint32_t error;
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bool finished;
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QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
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};
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struct VirtIOGPUBase {
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VirtIODevice parent_obj;
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Error *migration_blocker;
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struct virtio_gpu_base_conf conf;
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struct virtio_gpu_config virtio_config;
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const GraphicHwOps *hw_ops;
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int renderer_blocked;
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int enable;
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struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
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int enabled_output_bitmask;
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struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
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};
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struct VirtIOGPUBaseClass {
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VirtioDeviceClass parent;
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void (*gl_flushed)(VirtIOGPUBase *g);
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};
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#define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \
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DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \
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DEFINE_PROP_BIT("edid", _state, _conf.flags, \
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VIRTIO_GPU_FLAG_EDID_ENABLED, true), \
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DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1024), \
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DEFINE_PROP_UINT32("yres", _state, _conf.yres, 768)
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struct VirtIOGPU {
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VirtIOGPUBase parent_obj;
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uint64_t conf_max_hostmem;
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VirtQueue *ctrl_vq;
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VirtQueue *cursor_vq;
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QEMUBH *ctrl_bh;
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QEMUBH *cursor_bh;
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QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
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QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
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QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
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uint64_t hostmem;
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bool processing_cmdq;
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bool renderer_inited;
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bool renderer_reset;
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QEMUTimer *fence_poll;
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QEMUTimer *print_stats;
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uint32_t inflight;
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struct {
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uint32_t max_inflight;
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uint32_t requests;
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uint32_t req_3d;
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uint32_t bytes_3d;
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} stats;
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};
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struct VirtIOGPUClass {
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VirtIOGPUBaseClass parent;
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void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq);
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void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
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void (*update_cursor_data)(VirtIOGPU *g,
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struct virtio_gpu_scanout *s,
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uint32_t resource_id);
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};
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struct VirtIOGPUGL {
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struct VirtIOGPU parent_obj;
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};
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struct VhostUserGPU {
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VirtIOGPUBase parent_obj;
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VhostUserBackend *vhost;
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int vhost_gpu_fd; /* closed by the chardev */
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CharBackend vhost_chr;
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QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS];
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bool backend_blocked;
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};
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#define VIRTIO_GPU_FILL_CMD(out) do { \
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size_t s; \
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s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
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&out, sizeof(out)); \
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if (s != sizeof(out)) { \
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qemu_log_mask(LOG_GUEST_ERROR, \
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"%s: command size incorrect %zu vs %zu\n", \
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__func__, s, sizeof(out)); \
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return; \
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} \
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} while (0)
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/* virtio-gpu-base.c */
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bool virtio_gpu_base_device_realize(DeviceState *qdev,
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VirtIOHandleOutput ctrl_cb,
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VirtIOHandleOutput cursor_cb,
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Error **errp);
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void virtio_gpu_base_reset(VirtIOGPUBase *g);
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void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
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struct virtio_gpu_resp_display_info *dpy_info);
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/* virtio-gpu.c */
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void virtio_gpu_ctrl_response(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd,
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struct virtio_gpu_ctrl_hdr *resp,
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size_t resp_len);
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void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd,
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enum virtio_gpu_ctrl_type type);
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void virtio_gpu_get_display_info(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd);
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void virtio_gpu_get_edid(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd);
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int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
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struct virtio_gpu_resource_attach_backing *ab,
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struct virtio_gpu_ctrl_command *cmd,
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uint64_t **addr, struct iovec **iov,
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uint32_t *niov);
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void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
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struct iovec *iov, uint32_t count);
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void virtio_gpu_process_cmdq(VirtIOGPU *g);
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void virtio_gpu_device_realize(DeviceState *qdev, Error **errp);
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void virtio_gpu_reset(VirtIODevice *vdev);
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void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
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void virtio_gpu_update_cursor_data(VirtIOGPU *g,
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struct virtio_gpu_scanout *s,
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uint32_t resource_id);
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/* virtio-gpu-3d.c */
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void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd);
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void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
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void virtio_gpu_virgl_reset(VirtIOGPU *g);
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int virtio_gpu_virgl_init(VirtIOGPU *g);
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int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);
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#endif
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