843 lines
24 KiB
C
843 lines
24 KiB
C
/*
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* DEC 21272 (TSUNAMI/TYPHOON) chipset emulation.
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*
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* Written by Richard Henderson.
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*/
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#include "cpu.h"
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#include "hw/hw.h"
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#include "hw/devices.h"
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#include "sysemu/sysemu.h"
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#include "alpha_sys.h"
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#include "exec/address-spaces.h"
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#define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
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typedef struct TyphoonCchip {
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MemoryRegion region;
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uint64_t misc;
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uint64_t drir;
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uint64_t dim[4];
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uint32_t iic[4];
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AlphaCPU *cpu[4];
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} TyphoonCchip;
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typedef struct TyphoonWindow {
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uint32_t base_addr;
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uint32_t mask;
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uint32_t translated_base_pfn;
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} TyphoonWindow;
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typedef struct TyphoonPchip {
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MemoryRegion region;
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MemoryRegion reg_iack;
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MemoryRegion reg_mem;
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MemoryRegion reg_io;
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MemoryRegion reg_conf;
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uint64_t ctl;
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TyphoonWindow win[4];
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} TyphoonPchip;
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#define TYPHOON_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE)
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typedef struct TyphoonState {
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PCIHostState parent_obj;
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TyphoonCchip cchip;
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TyphoonPchip pchip;
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MemoryRegion dchip_region;
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MemoryRegion ram_region;
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/* QEMU emulation state. */
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uint32_t latch_tmp;
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} TyphoonState;
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/* Called when one of DRIR or DIM changes. */
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static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)
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{
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/* If there are any non-masked interrupts, tell the cpu. */
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if (cpu != NULL) {
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CPUState *cs = CPU(cpu);
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if (req) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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}
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static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
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{
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CPUState *cpu = current_cpu;
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TyphoonState *s = opaque;
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uint64_t ret = 0;
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if (addr & 4) {
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return s->latch_tmp;
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}
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switch (addr) {
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case 0x0000:
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/* CSC: Cchip System Configuration Register. */
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/* All sorts of data here; probably the only thing relevant is
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PIP<14> Pchip 1 Present = 0. */
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break;
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case 0x0040:
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/* MTR: Memory Timing Register. */
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/* All sorts of stuff related to real DRAM. */
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break;
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case 0x0080:
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/* MISC: Miscellaneous Register. */
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ret = s->cchip.misc | (cpu->cpu_index & 3);
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break;
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case 0x00c0:
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/* MPD: Memory Presence Detect Register. */
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break;
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case 0x0100: /* AAR0 */
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case 0x0140: /* AAR1 */
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case 0x0180: /* AAR2 */
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case 0x01c0: /* AAR3 */
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/* AAR: Array Address Register. */
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/* All sorts of information about DRAM. */
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break;
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case 0x0200:
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/* DIM0: Device Interrupt Mask Register, CPU0. */
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ret = s->cchip.dim[0];
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break;
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case 0x0240:
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/* DIM1: Device Interrupt Mask Register, CPU1. */
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ret = s->cchip.dim[1];
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break;
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case 0x0280:
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/* DIR0: Device Interrupt Request Register, CPU0. */
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ret = s->cchip.dim[0] & s->cchip.drir;
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break;
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case 0x02c0:
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/* DIR1: Device Interrupt Request Register, CPU1. */
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ret = s->cchip.dim[1] & s->cchip.drir;
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break;
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case 0x0300:
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/* DRIR: Device Raw Interrupt Request Register. */
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ret = s->cchip.drir;
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break;
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case 0x0340:
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/* PRBEN: Probe Enable Register. */
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break;
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case 0x0380:
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/* IIC0: Interval Ignore Count Register, CPU0. */
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ret = s->cchip.iic[0];
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break;
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case 0x03c0:
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/* IIC1: Interval Ignore Count Register, CPU1. */
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ret = s->cchip.iic[1];
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break;
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case 0x0400: /* MPR0 */
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case 0x0440: /* MPR1 */
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case 0x0480: /* MPR2 */
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case 0x04c0: /* MPR3 */
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/* MPR: Memory Programming Register. */
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break;
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case 0x0580:
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/* TTR: TIGbus Timing Register. */
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/* All sorts of stuff related to interrupt delivery timings. */
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break;
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case 0x05c0:
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/* TDR: TIGbug Device Timing Register. */
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break;
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case 0x0600:
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/* DIM2: Device Interrupt Mask Register, CPU2. */
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ret = s->cchip.dim[2];
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break;
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case 0x0640:
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/* DIM3: Device Interrupt Mask Register, CPU3. */
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ret = s->cchip.dim[3];
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break;
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case 0x0680:
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/* DIR2: Device Interrupt Request Register, CPU2. */
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ret = s->cchip.dim[2] & s->cchip.drir;
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break;
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case 0x06c0:
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/* DIR3: Device Interrupt Request Register, CPU3. */
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ret = s->cchip.dim[3] & s->cchip.drir;
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break;
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case 0x0700:
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/* IIC2: Interval Ignore Count Register, CPU2. */
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ret = s->cchip.iic[2];
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break;
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case 0x0740:
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/* IIC3: Interval Ignore Count Register, CPU3. */
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ret = s->cchip.iic[3];
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break;
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case 0x0780:
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/* PWR: Power Management Control. */
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break;
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case 0x0c00: /* CMONCTLA */
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case 0x0c40: /* CMONCTLB */
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case 0x0c80: /* CMONCNT01 */
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case 0x0cc0: /* CMONCNT23 */
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break;
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default:
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cpu_unassigned_access(cpu, addr, false, false, 0, size);
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return -1;
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}
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s->latch_tmp = ret >> 32;
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return ret;
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}
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static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
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{
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/* Skip this. It's all related to DRAM timing and setup. */
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return 0;
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}
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static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
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{
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TyphoonState *s = opaque;
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uint64_t ret = 0;
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if (addr & 4) {
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return s->latch_tmp;
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}
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switch (addr) {
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case 0x0000:
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/* WSBA0: Window Space Base Address Register. */
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ret = s->pchip.win[0].base_addr;
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break;
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case 0x0040:
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/* WSBA1 */
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ret = s->pchip.win[1].base_addr;
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break;
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case 0x0080:
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/* WSBA2 */
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ret = s->pchip.win[2].base_addr;
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break;
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case 0x00c0:
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/* WSBA3 */
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ret = s->pchip.win[3].base_addr;
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break;
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case 0x0100:
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/* WSM0: Window Space Mask Register. */
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ret = s->pchip.win[0].mask;
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break;
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case 0x0140:
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/* WSM1 */
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ret = s->pchip.win[1].mask;
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break;
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case 0x0180:
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/* WSM2 */
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ret = s->pchip.win[2].mask;
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break;
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case 0x01c0:
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/* WSM3 */
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ret = s->pchip.win[3].mask;
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break;
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case 0x0200:
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/* TBA0: Translated Base Address Register. */
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ret = (uint64_t)s->pchip.win[0].translated_base_pfn << 10;
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break;
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case 0x0240:
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/* TBA1 */
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ret = (uint64_t)s->pchip.win[1].translated_base_pfn << 10;
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break;
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case 0x0280:
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/* TBA2 */
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ret = (uint64_t)s->pchip.win[2].translated_base_pfn << 10;
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break;
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case 0x02c0:
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/* TBA3 */
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ret = (uint64_t)s->pchip.win[3].translated_base_pfn << 10;
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break;
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case 0x0300:
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/* PCTL: Pchip Control Register. */
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ret = s->pchip.ctl;
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break;
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case 0x0340:
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/* PLAT: Pchip Master Latency Register. */
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break;
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case 0x03c0:
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/* PERROR: Pchip Error Register. */
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break;
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case 0x0400:
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/* PERRMASK: Pchip Error Mask Register. */
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break;
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case 0x0440:
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/* PERRSET: Pchip Error Set Register. */
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break;
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case 0x0480:
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/* TLBIV: Translation Buffer Invalidate Virtual Register (WO). */
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break;
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case 0x04c0:
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/* TLBIA: Translation Buffer Invalidate All Register (WO). */
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break;
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case 0x0500: /* PMONCTL */
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case 0x0540: /* PMONCNT */
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case 0x0800: /* SPRST */
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break;
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default:
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cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
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return -1;
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}
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s->latch_tmp = ret >> 32;
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return ret;
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}
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static void cchip_write(void *opaque, hwaddr addr,
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uint64_t v32, unsigned size)
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{
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TyphoonState *s = opaque;
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uint64_t val, oldval, newval;
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if (addr & 4) {
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val = v32 << 32 | s->latch_tmp;
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addr ^= 4;
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} else {
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s->latch_tmp = v32;
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return;
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}
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switch (addr) {
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case 0x0000:
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/* CSC: Cchip System Configuration Register. */
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/* All sorts of data here; nothing relevant RW. */
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break;
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case 0x0040:
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/* MTR: Memory Timing Register. */
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/* All sorts of stuff related to real DRAM. */
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break;
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case 0x0080:
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/* MISC: Miscellaneous Register. */
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newval = oldval = s->cchip.misc;
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newval &= ~(val & 0x10000ff0); /* W1C fields */
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if (val & 0x100000) {
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newval &= ~0xff0000ull; /* ACL clears ABT and ABW */
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} else {
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newval |= val & 0x00f00000; /* ABT field is W1S */
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if ((newval & 0xf0000) == 0) {
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newval |= val & 0xf0000; /* ABW field is W1S iff zero */
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}
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}
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newval |= (val & 0xf000) >> 4; /* IPREQ field sets IPINTR. */
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newval &= ~0xf0000000000ull; /* WO and RW fields */
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newval |= val & 0xf0000000000ull;
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s->cchip.misc = newval;
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/* Pass on changes to IPI and ITI state. */
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if ((newval ^ oldval) & 0xff0) {
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int i;
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for (i = 0; i < 4; ++i) {
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AlphaCPU *cpu = s->cchip.cpu[i];
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if (cpu != NULL) {
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CPUState *cs = CPU(cpu);
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/* IPI can be either cleared or set by the write. */
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if (newval & (1 << (i + 8))) {
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cpu_interrupt(cs, CPU_INTERRUPT_SMP);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP);
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}
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/* ITI can only be cleared by the write. */
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if ((newval & (1 << (i + 4))) == 0) {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER);
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}
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}
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}
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}
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break;
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case 0x00c0:
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/* MPD: Memory Presence Detect Register. */
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break;
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case 0x0100: /* AAR0 */
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case 0x0140: /* AAR1 */
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case 0x0180: /* AAR2 */
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case 0x01c0: /* AAR3 */
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/* AAR: Array Address Register. */
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/* All sorts of information about DRAM. */
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break;
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case 0x0200: /* DIM0 */
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/* DIM: Device Interrupt Mask Register, CPU0. */
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s->cchip.dim[0] = val;
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cpu_irq_change(s->cchip.cpu[0], val & s->cchip.drir);
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break;
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case 0x0240: /* DIM1 */
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/* DIM: Device Interrupt Mask Register, CPU1. */
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s->cchip.dim[0] = val;
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cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir);
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break;
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case 0x0280: /* DIR0 (RO) */
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case 0x02c0: /* DIR1 (RO) */
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case 0x0300: /* DRIR (RO) */
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break;
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case 0x0340:
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/* PRBEN: Probe Enable Register. */
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break;
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case 0x0380: /* IIC0 */
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s->cchip.iic[0] = val & 0xffffff;
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break;
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case 0x03c0: /* IIC1 */
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s->cchip.iic[1] = val & 0xffffff;
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break;
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case 0x0400: /* MPR0 */
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case 0x0440: /* MPR1 */
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case 0x0480: /* MPR2 */
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case 0x04c0: /* MPR3 */
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/* MPR: Memory Programming Register. */
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break;
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case 0x0580:
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/* TTR: TIGbus Timing Register. */
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/* All sorts of stuff related to interrupt delivery timings. */
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break;
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case 0x05c0:
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/* TDR: TIGbug Device Timing Register. */
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break;
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case 0x0600:
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/* DIM2: Device Interrupt Mask Register, CPU2. */
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s->cchip.dim[2] = val;
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cpu_irq_change(s->cchip.cpu[2], val & s->cchip.drir);
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break;
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case 0x0640:
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/* DIM3: Device Interrupt Mask Register, CPU3. */
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s->cchip.dim[3] = val;
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cpu_irq_change(s->cchip.cpu[3], val & s->cchip.drir);
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break;
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case 0x0680: /* DIR2 (RO) */
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case 0x06c0: /* DIR3 (RO) */
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break;
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case 0x0700: /* IIC2 */
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s->cchip.iic[2] = val & 0xffffff;
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break;
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case 0x0740: /* IIC3 */
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s->cchip.iic[3] = val & 0xffffff;
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break;
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case 0x0780:
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/* PWR: Power Management Control. */
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break;
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case 0x0c00: /* CMONCTLA */
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case 0x0c40: /* CMONCTLB */
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case 0x0c80: /* CMONCNT01 */
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case 0x0cc0: /* CMONCNT23 */
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break;
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default:
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cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
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return;
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}
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}
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static void dchip_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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/* Skip this. It's all related to DRAM timing and setup. */
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}
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static void pchip_write(void *opaque, hwaddr addr,
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uint64_t v32, unsigned size)
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{
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TyphoonState *s = opaque;
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uint64_t val, oldval;
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if (addr & 4) {
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val = v32 << 32 | s->latch_tmp;
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addr ^= 4;
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} else {
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s->latch_tmp = v32;
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return;
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}
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switch (addr) {
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case 0x0000:
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/* WSBA0: Window Space Base Address Register. */
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s->pchip.win[0].base_addr = val;
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break;
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case 0x0040:
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/* WSBA1 */
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s->pchip.win[1].base_addr = val;
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break;
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case 0x0080:
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/* WSBA2 */
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s->pchip.win[2].base_addr = val;
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break;
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case 0x00c0:
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/* WSBA3 */
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s->pchip.win[3].base_addr = val;
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break;
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case 0x0100:
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/* WSM0: Window Space Mask Register. */
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s->pchip.win[0].mask = val;
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break;
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case 0x0140:
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/* WSM1 */
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s->pchip.win[1].mask = val;
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break;
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case 0x0180:
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/* WSM2 */
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s->pchip.win[2].mask = val;
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break;
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case 0x01c0:
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/* WSM3 */
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s->pchip.win[3].mask = val;
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break;
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case 0x0200:
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/* TBA0: Translated Base Address Register. */
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s->pchip.win[0].translated_base_pfn = val >> 10;
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break;
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case 0x0240:
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/* TBA1 */
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s->pchip.win[1].translated_base_pfn = val >> 10;
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break;
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case 0x0280:
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/* TBA2 */
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s->pchip.win[2].translated_base_pfn = val >> 10;
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break;
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case 0x02c0:
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/* TBA3 */
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s->pchip.win[3].translated_base_pfn = val >> 10;
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break;
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|
case 0x0300:
|
|
/* PCTL: Pchip Control Register. */
|
|
oldval = s->pchip.ctl;
|
|
oldval &= ~0x00001cff0fc7ffull; /* RW fields */
|
|
oldval |= val & 0x00001cff0fc7ffull;
|
|
|
|
s->pchip.ctl = oldval;
|
|
break;
|
|
|
|
case 0x0340:
|
|
/* PLAT: Pchip Master Latency Register. */
|
|
break;
|
|
case 0x03c0:
|
|
/* PERROR: Pchip Error Register. */
|
|
break;
|
|
case 0x0400:
|
|
/* PERRMASK: Pchip Error Mask Register. */
|
|
break;
|
|
case 0x0440:
|
|
/* PERRSET: Pchip Error Set Register. */
|
|
break;
|
|
|
|
case 0x0480:
|
|
/* TLBIV: Translation Buffer Invalidate Virtual Register. */
|
|
break;
|
|
|
|
case 0x04c0:
|
|
/* TLBIA: Translation Buffer Invalidate All Register (WO). */
|
|
break;
|
|
|
|
case 0x0500:
|
|
/* PMONCTL */
|
|
case 0x0540:
|
|
/* PMONCNT */
|
|
case 0x0800:
|
|
/* SPRST */
|
|
break;
|
|
|
|
default:
|
|
cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps cchip_ops = {
|
|
.read = cchip_read,
|
|
.write = cchip_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4, /* ??? Should be 8. */
|
|
.max_access_size = 8,
|
|
},
|
|
.impl = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
};
|
|
|
|
static const MemoryRegionOps dchip_ops = {
|
|
.read = dchip_read,
|
|
.write = dchip_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4, /* ??? Should be 8. */
|
|
.max_access_size = 8,
|
|
},
|
|
.impl = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 8,
|
|
},
|
|
};
|
|
|
|
static const MemoryRegionOps pchip_ops = {
|
|
.read = pchip_read,
|
|
.write = pchip_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4, /* ??? Should be 8. */
|
|
.max_access_size = 8,
|
|
},
|
|
.impl = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
};
|
|
|
|
static void typhoon_set_irq(void *opaque, int irq, int level)
|
|
{
|
|
TyphoonState *s = opaque;
|
|
uint64_t drir;
|
|
int i;
|
|
|
|
/* Set/Reset the bit in CCHIP.DRIR based on IRQ+LEVEL. */
|
|
drir = s->cchip.drir;
|
|
if (level) {
|
|
drir |= 1ull << irq;
|
|
} else {
|
|
drir &= ~(1ull << irq);
|
|
}
|
|
s->cchip.drir = drir;
|
|
|
|
for (i = 0; i < 4; ++i) {
|
|
cpu_irq_change(s->cchip.cpu[i], s->cchip.dim[i] & drir);
|
|
}
|
|
}
|
|
|
|
static void typhoon_set_isa_irq(void *opaque, int irq, int level)
|
|
{
|
|
typhoon_set_irq(opaque, 55, level);
|
|
}
|
|
|
|
static void typhoon_set_timer_irq(void *opaque, int irq, int level)
|
|
{
|
|
TyphoonState *s = opaque;
|
|
int i;
|
|
|
|
/* Thankfully, the mc146818rtc code doesn't track the IRQ state,
|
|
and so we don't have to worry about missing interrupts just
|
|
because we never actually ACK the interrupt. Just ignore any
|
|
case of the interrupt level going low. */
|
|
if (level == 0) {
|
|
return;
|
|
}
|
|
|
|
/* Deliver the interrupt to each CPU, considering each CPU's IIC. */
|
|
for (i = 0; i < 4; ++i) {
|
|
AlphaCPU *cpu = s->cchip.cpu[i];
|
|
if (cpu != NULL) {
|
|
uint32_t iic = s->cchip.iic[i];
|
|
|
|
/* ??? The verbage in Section 10.2.2.10 isn't 100% clear.
|
|
Bit 24 is the OverFlow bit, RO, and set when the count
|
|
decrements past 0. When is OF cleared? My guess is that
|
|
OF is actually cleared when the IIC is written, and that
|
|
the ICNT field always decrements. At least, that's an
|
|
interpretation that makes sense, and "allows the CPU to
|
|
determine exactly how mant interval timer ticks were
|
|
skipped". At least within the next 4M ticks... */
|
|
|
|
iic = ((iic - 1) & 0x1ffffff) | (iic & 0x1000000);
|
|
s->cchip.iic[i] = iic;
|
|
|
|
if (iic & 0x1000000) {
|
|
/* Set the ITI bit for this cpu. */
|
|
s->cchip.misc |= 1 << (i + 4);
|
|
/* And signal the interrupt. */
|
|
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void typhoon_alarm_timer(void *opaque)
|
|
{
|
|
TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3);
|
|
int cpu = (uintptr_t)opaque & 3;
|
|
|
|
/* Set the ITI bit for this cpu. */
|
|
s->cchip.misc |= 1 << (cpu + 4);
|
|
cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER);
|
|
}
|
|
|
|
PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
|
|
qemu_irq *p_rtc_irq,
|
|
AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
|
|
{
|
|
const uint64_t MB = 1024 * 1024;
|
|
const uint64_t GB = 1024 * MB;
|
|
MemoryRegion *addr_space = get_system_memory();
|
|
MemoryRegion *addr_space_io = get_system_io();
|
|
DeviceState *dev;
|
|
TyphoonState *s;
|
|
PCIHostState *phb;
|
|
PCIBus *b;
|
|
int i;
|
|
|
|
dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);
|
|
qdev_init_nofail(dev);
|
|
|
|
s = TYPHOON_PCI_HOST_BRIDGE(dev);
|
|
phb = PCI_HOST_BRIDGE(dev);
|
|
|
|
/* Remember the CPUs so that we can deliver interrupts to them. */
|
|
for (i = 0; i < 4; i++) {
|
|
AlphaCPU *cpu = cpus[i];
|
|
s->cchip.cpu[i] = cpu;
|
|
if (cpu != NULL) {
|
|
cpu->alarm_timer = qemu_new_timer_ns(rtc_clock,
|
|
typhoon_alarm_timer,
|
|
(void *)((uintptr_t)s + i));
|
|
}
|
|
}
|
|
|
|
*p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1);
|
|
|
|
/* Main memory region, 0x00.0000.0000. Real hardware supports 32GB,
|
|
but the address space hole reserved at this point is 8TB. */
|
|
memory_region_init_ram(&s->ram_region, OBJECT(s), "ram", ram_size);
|
|
vmstate_register_ram_global(&s->ram_region);
|
|
memory_region_add_subregion(addr_space, 0, &s->ram_region);
|
|
|
|
/* TIGbus, 0x801.0000.0000, 1GB. */
|
|
/* ??? The TIGbus is used for delivering interrupts, and access to
|
|
the flash ROM. I'm not sure that we need to implement it at all. */
|
|
|
|
/* Pchip0 CSRs, 0x801.8000.0000, 256MB. */
|
|
memory_region_init_io(&s->pchip.region, OBJECT(s), &pchip_ops, s, "pchip0",
|
|
256*MB);
|
|
memory_region_add_subregion(addr_space, 0x80180000000ULL,
|
|
&s->pchip.region);
|
|
|
|
/* Cchip CSRs, 0x801.A000.0000, 256MB. */
|
|
memory_region_init_io(&s->cchip.region, OBJECT(s), &cchip_ops, s, "cchip0",
|
|
256*MB);
|
|
memory_region_add_subregion(addr_space, 0x801a0000000ULL,
|
|
&s->cchip.region);
|
|
|
|
/* Dchip CSRs, 0x801.B000.0000, 256MB. */
|
|
memory_region_init_io(&s->dchip_region, OBJECT(s), &dchip_ops, s, "dchip0",
|
|
256*MB);
|
|
memory_region_add_subregion(addr_space, 0x801b0000000ULL,
|
|
&s->dchip_region);
|
|
|
|
/* Pchip0 PCI memory, 0x800.0000.0000, 4GB. */
|
|
memory_region_init(&s->pchip.reg_mem, OBJECT(s), "pci0-mem", 4*GB);
|
|
memory_region_add_subregion(addr_space, 0x80000000000ULL,
|
|
&s->pchip.reg_mem);
|
|
|
|
/* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB. */
|
|
/* ??? Ideally we drop the "system" i/o space on the floor and give the
|
|
PCI subsystem the full address space reserved by the chipset.
|
|
We can't do that until the MEM and IO paths in memory.c are unified. */
|
|
memory_region_init_io(&s->pchip.reg_io, OBJECT(s), &alpha_pci_bw_io_ops,
|
|
NULL, "pci0-io", 32*MB);
|
|
memory_region_add_subregion(addr_space, 0x801fc000000ULL,
|
|
&s->pchip.reg_io);
|
|
|
|
b = pci_register_bus(dev, "pci",
|
|
typhoon_set_irq, sys_map_irq, s,
|
|
&s->pchip.reg_mem, addr_space_io, 0, 64, TYPE_PCI_BUS);
|
|
phb->bus = b;
|
|
|
|
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
|
|
memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, b,
|
|
"pci0-iack", 64*MB);
|
|
memory_region_add_subregion(addr_space, 0x801f8000000ULL,
|
|
&s->pchip.reg_iack);
|
|
|
|
/* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB. */
|
|
memory_region_init_io(&s->pchip.reg_conf, OBJECT(s), &alpha_pci_conf1_ops, b,
|
|
"pci0-conf", 16*MB);
|
|
memory_region_add_subregion(addr_space, 0x801fe000000ULL,
|
|
&s->pchip.reg_conf);
|
|
|
|
/* For the record, these are the mappings for the second PCI bus.
|
|
We can get away with not implementing them because we indicate
|
|
via the Cchip.CSC<PIP> bit that Pchip1 is not present. */
|
|
/* Pchip1 PCI memory, 0x802.0000.0000, 4GB. */
|
|
/* Pchip1 CSRs, 0x802.8000.0000, 256MB. */
|
|
/* Pchip1 PCI special/interrupt acknowledge, 0x802.F800.0000, 64MB. */
|
|
/* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB. */
|
|
/* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB. */
|
|
|
|
/* Init the ISA bus. */
|
|
/* ??? Technically there should be a cy82c693ub pci-isa bridge. */
|
|
{
|
|
qemu_irq isa_pci_irq, *isa_irqs;
|
|
|
|
*isa_bus = isa_bus_new(NULL, addr_space_io);
|
|
isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1);
|
|
isa_irqs = i8259_init(*isa_bus, isa_pci_irq);
|
|
isa_bus_irqs(*isa_bus, isa_irqs);
|
|
}
|
|
|
|
return b;
|
|
}
|
|
|
|
static int typhoon_pcihost_init(SysBusDevice *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void typhoon_pcihost_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = typhoon_pcihost_init;
|
|
dc->no_user = 1;
|
|
}
|
|
|
|
static const TypeInfo typhoon_pcihost_info = {
|
|
.name = TYPE_TYPHOON_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(TyphoonState),
|
|
.class_init = typhoon_pcihost_class_init,
|
|
};
|
|
|
|
static void typhoon_register_types(void)
|
|
{
|
|
type_register_static(&typhoon_pcihost_info);
|
|
}
|
|
|
|
type_init(typhoon_register_types)
|