Bin Meng 49093916d3 hw/riscv: sifive_u: Sort the SoC memmap table entries ...

Move the flash and DRAM to the end of the SoC memmap table.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2020-06-19 08:25:27 -07:00

..

boot.c

…

Kconfig

hw/char: Initial commit of Ibex UART

2020-06-19 08:24:07 -07:00

Makefile.objs

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opentitan.c

hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions

2020-06-19 08:24:07 -07:00

riscv_hart.c

qdev: Convert bus-less devices to qdev_realize() with Coccinelle

2020-06-15 22:06:04 +02:00

riscv_htif.c

…

sifive_clint.c

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sifive_e_prci.c

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sifive_e.c

hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004

2020-06-19 08:25:27 -07:00

sifive_gpio.c

hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

2020-06-19 08:25:27 -07:00

sifive_plic.c

…

sifive_test.c

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sifive_u_otp.c

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sifive_u_prci.c

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sifive_u.c

hw/riscv: sifive_u: Sort the SoC memmap table entries

2020-06-19 08:25:27 -07:00

sifive_uart.c

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spike.c

sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1

2020-06-15 22:06:04 +02:00

trace-events

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virt.c

sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1

2020-06-15 22:06:04 +02:00