420557e898
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1085 c046a42c-6fe2-441c-8c8c-71466251a162
222 lines
8.0 KiB
C
222 lines
8.0 KiB
C
/*
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* QEMU SPARC iommu emulation
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/* debug iommu */
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//#define DEBUG_IOMMU
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/* The IOMMU registers occupy three pages in IO space. */
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struct iommu_regs {
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/* First page */
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volatile unsigned long control; /* IOMMU control */
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volatile unsigned long base; /* Physical base of iopte page table */
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volatile unsigned long _unused1[3];
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volatile unsigned long tlbflush; /* write only */
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volatile unsigned long pageflush; /* write only */
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volatile unsigned long _unused2[1017];
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/* Second page */
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volatile unsigned long afsr; /* Async-fault status register */
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volatile unsigned long afar; /* Async-fault physical address */
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volatile unsigned long _unused3[2];
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volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
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volatile unsigned long sbuscfg1;
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volatile unsigned long sbuscfg2;
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volatile unsigned long sbuscfg3;
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volatile unsigned long mfsr; /* Memory-fault status register */
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volatile unsigned long mfar; /* Memory-fault physical address */
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volatile unsigned long _unused4[1014];
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/* Third page */
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volatile unsigned long mid; /* IOMMU module-id */
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};
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#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
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#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
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#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
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#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
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#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
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#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
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#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
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#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
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#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
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#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
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#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
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#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
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#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
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#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
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#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
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#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
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#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
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#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
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#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
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#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
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#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
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#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
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#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
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#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
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produced by this device as pure
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physical. */
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#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
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#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
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#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
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#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
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#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
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on the even word of the access, low bit
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indicated odd word caused the parity error */
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#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
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#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
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#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
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#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
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#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
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#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
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#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
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#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
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#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
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#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
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/* The format of an iopte in the page tables */
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#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
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#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
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#define IOPTE_WRITE 0x00000004 /* Writeable */
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#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
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#define IOPTE_WAZ 0x00000001 /* Write as zeros */
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#define PHYS_JJ_IOMMU 0x10000000 /* First page of sun4m IOMMU */
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define PAGE_MASK (PAGE_SIZE - 1)
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typedef struct IOMMUState {
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uint32_t regs[sizeof(struct iommu_regs)];
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} IOMMUState;
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static IOMMUState *ps;
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static int iommu_io_memory;
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static void iommu_reset(IOMMUState *s)
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{
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}
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static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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IOMMUState *s = opaque;
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uint32_t saddr;
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saddr = (addr - PHYS_JJ_IOMMU) >> 2;
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switch (saddr) {
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default:
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return s->regs[saddr];
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break;
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}
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return 0;
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}
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static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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IOMMUState *s = opaque;
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uint32_t saddr;
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saddr = (addr - PHYS_JJ_IOMMU) >> 2;
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switch (saddr) {
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default:
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s->regs[saddr] = val;
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break;
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}
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}
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static CPUReadMemoryFunc *iommu_mem_read[3] = {
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iommu_mem_readw,
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iommu_mem_readw,
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iommu_mem_readw,
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};
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static CPUWriteMemoryFunc *iommu_mem_write[3] = {
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iommu_mem_writew,
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iommu_mem_writew,
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iommu_mem_writew,
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};
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uint32_t iommu_translate(uint32_t addr)
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{
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uint32_t *iopte = (void *)(ps->regs[1] << 4), pa, iostart;
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switch (ps->regs[0] & IOMMU_CTRL_RNGE) {
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case IOMMU_RNGE_16MB:
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iostart = 0xff000000;
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break;
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case IOMMU_RNGE_32MB:
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iostart = 0xfe000000;
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break;
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case IOMMU_RNGE_64MB:
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iostart = 0xfc000000;
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break;
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case IOMMU_RNGE_128MB:
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iostart = 0xf8000000;
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break;
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case IOMMU_RNGE_256MB:
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iostart = 0xf0000000;
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break;
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case IOMMU_RNGE_512MB:
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iostart = 0xe0000000;
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break;
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case IOMMU_RNGE_1GB:
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iostart = 0xc0000000;
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break;
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default:
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case IOMMU_RNGE_2GB:
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iostart = 0x80000000;
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break;
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}
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iopte += ((addr - iostart) >> PAGE_SHIFT);
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cpu_physical_memory_rw((uint32_t)iopte, (void *) &pa, 4, 0);
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bswap32s(&pa);
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pa = (pa & IOPTE_PAGE) << 4; /* Loose higher bits of 36 */
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//return pa + PAGE_SIZE;
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return pa + (addr & PAGE_MASK);
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}
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void iommu_init()
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{
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IOMMUState *s;
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s = qemu_mallocz(sizeof(IOMMUState));
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if (!s)
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return;
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iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
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cpu_register_physical_memory(PHYS_JJ_IOMMU, sizeof(struct iommu_regs),
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iommu_io_memory);
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iommu_reset(s);
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ps = s;
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}
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