3023f3329d
Patch 5/7 This patch changes the graphical_console_init function to return an allocated DisplayState instead of a QEMUConsole. This patch contains just the graphical_console_init change and few other modifications mainly in console.c and vl.c. It was necessary to move the display frontends (e.g. sdl and vnc) initialization after machine->init in vl.c. This patch does *not* include any required changes to any device, these changes come with the following patches. Patch 6/7 This patch changes the QEMUMachine init functions not to take a DisplayState as an argument because is not needed any more; In few places the graphic hardware initialization function was called only if DisplayState was not NULL, now they are always called. Apart from these cases, the rest are all mechanical substitutions. Patch 7/7 This patch updates the graphic device code to use the new graphical_console_init function. As for the previous patch, in few places graphical_console_init was called only if DisplayState was not NULL, now it is always called. Apart from these cases, the rest are all mechanical substitutions. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6344 c046a42c-6fe2-441c-8c8c-71466251a162
72 lines
2.5 KiB
C
72 lines
2.5 KiB
C
#ifndef SUN4M_H
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#define SUN4M_H
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/* Devices used by sparc32 system. */
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/* iommu.c */
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void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq);
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void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
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uint8_t *buf, int len, int is_write);
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static inline void sparc_iommu_memory_read(void *opaque,
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target_phys_addr_t addr,
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uint8_t *buf, int len)
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{
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sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
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}
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static inline void sparc_iommu_memory_write(void *opaque,
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target_phys_addr_t addr,
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uint8_t *buf, int len)
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{
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sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
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}
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/* tcx.c */
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void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
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unsigned long vram_offset, int vram_size, int width, int height,
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int depth);
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/* slavio_intctl.c */
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void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
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const uint32_t *intbit_to_level,
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qemu_irq **irq, qemu_irq **cpu_irq,
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qemu_irq **parent_irq, unsigned int cputimer);
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void slavio_pic_info(void *opaque);
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void slavio_irq_info(void *opaque);
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/* sbi.c */
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void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
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qemu_irq **parent_irq);
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/* sun4c_intctl.c */
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void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
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qemu_irq *parent_irq);
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void sun4c_pic_info(void *opaque);
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void sun4c_irq_info(void *opaque);
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/* slavio_timer.c */
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void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
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qemu_irq *cpu_irqs, unsigned int num_cpus);
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/* slavio_misc.c */
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void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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target_phys_addr_t aux1_base,
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target_phys_addr_t aux2_base, qemu_irq irq,
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qemu_irq cpu_halt, qemu_irq **fdc_tc);
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void slavio_set_power_fail(void *opaque, int power_failing);
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/* cs4231.c */
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void cs_init(target_phys_addr_t base, int irq, void *intctl);
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/* sparc32_dma.c */
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#include "sparc32_dma.h"
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/* pcnet.c */
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void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
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qemu_irq irq, qemu_irq *reset);
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/* eccmemctl.c */
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void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);
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#endif
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