47b43a1f41
Many headers are used only in a single directory. These can be kept in hw/. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
594 lines
18 KiB
C
594 lines
18 KiB
C
/*
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* Toshiba TC6393XB I/O Controller.
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* Found in Sharp Zaurus SL-6000 (tosa) or some
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* Toshiba e-Series PDAs.
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*
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* Most features are currently unsupported!!!
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*
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* This code is licensed under the GNU GPL v2.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw/hw.h"
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#include "hw/arm/devices.h"
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#include "hw/block/flash.h"
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#include "ui/console.h"
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#include "ui/pixel_ops.h"
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#include "sysemu/blockdev.h"
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#define IRQ_TC6393_NAND 0
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#define IRQ_TC6393_MMC 1
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#define IRQ_TC6393_OHCI 2
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#define IRQ_TC6393_SERIAL 3
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#define IRQ_TC6393_FB 4
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#define TC6393XB_NR_IRQS 8
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#define TC6393XB_GPIOS 16
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#define SCR_REVID 0x08 /* b Revision ID */
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#define SCR_ISR 0x50 /* b Interrupt Status */
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#define SCR_IMR 0x52 /* b Interrupt Mask */
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#define SCR_IRR 0x54 /* b Interrupt Routing */
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#define SCR_GPER 0x60 /* w GP Enable */
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#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
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#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
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#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
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#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
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#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
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#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
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#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
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#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
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#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
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#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
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#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
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#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
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#define SCR_CCR 0x98 /* w Clock Control */
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#define SCR_PLL2CR 0x9a /* w PLL2 Control */
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#define SCR_PLL1CR 0x9c /* l PLL1 Control */
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#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
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#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
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#define SCR_FER 0xe0 /* b Function Enable */
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#define SCR_MCR 0xe4 /* w Mode Control */
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#define SCR_CONFIG 0xfc /* b Configuration Control */
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#define SCR_DEBUG 0xff /* b Debug */
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#define NAND_CFG_COMMAND 0x04 /* w Command */
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#define NAND_CFG_BASE 0x10 /* l Control Base Address */
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#define NAND_CFG_INTP 0x3d /* b Interrupt Pin */
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#define NAND_CFG_INTE 0x48 /* b Int Enable */
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#define NAND_CFG_EC 0x4a /* b Event Control */
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#define NAND_CFG_ICC 0x4c /* b Internal Clock Control */
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#define NAND_CFG_ECCC 0x5b /* b ECC Control */
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#define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */
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#define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */
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#define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */
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#define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */
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#define NAND_DATA 0x00 /* l Data */
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#define NAND_MODE 0x04 /* b Mode */
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#define NAND_STATUS 0x05 /* b Status */
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#define NAND_ISR 0x06 /* b Interrupt Status */
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#define NAND_IMR 0x07 /* b Interrupt Mask */
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#define NAND_MODE_WP 0x80
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#define NAND_MODE_CE 0x10
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#define NAND_MODE_ALE 0x02
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#define NAND_MODE_CLE 0x01
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#define NAND_MODE_ECC_MASK 0x60
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#define NAND_MODE_ECC_EN 0x20
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#define NAND_MODE_ECC_READ 0x40
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#define NAND_MODE_ECC_RST 0x60
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struct TC6393xbState {
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq *sub_irqs;
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struct {
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uint8_t ISR;
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uint8_t IMR;
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uint8_t IRR;
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uint16_t GPER;
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uint8_t GPI_SR[3];
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uint8_t GPI_IMR[3];
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uint8_t GPI_EDER[3];
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uint8_t GPI_LIR[3];
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uint8_t GP_IARCR[3];
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uint8_t GP_IARLCR[3];
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uint8_t GPI_BCR[3];
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uint16_t GPA_IARCR;
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uint16_t GPA_IARLCR;
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uint16_t CCR;
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uint16_t PLL2CR;
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uint32_t PLL1CR;
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uint8_t DIARCR;
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uint8_t DBOCR;
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uint8_t FER;
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uint16_t MCR;
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uint8_t CONFIG;
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uint8_t DEBUG;
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} scr;
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uint32_t gpio_dir;
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uint32_t gpio_level;
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uint32_t prev_level;
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qemu_irq handler[TC6393XB_GPIOS];
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qemu_irq *gpio_in;
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struct {
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uint8_t mode;
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uint8_t isr;
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uint8_t imr;
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} nand;
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int nand_enable;
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uint32_t nand_phys;
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DeviceState *flash;
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ECCState ecc;
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QemuConsole *con;
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MemoryRegion vram;
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uint16_t *vram_ptr;
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uint32_t scr_width, scr_height; /* in pixels */
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qemu_irq l3v;
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unsigned blank : 1,
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blanked : 1;
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};
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qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
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{
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return s->gpio_in;
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}
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static void tc6393xb_gpio_set(void *opaque, int line, int level)
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{
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// TC6393xbState *s = opaque;
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if (line > TC6393XB_GPIOS) {
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printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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return;
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}
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// FIXME: how does the chip reflect the GPIO input level change?
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}
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void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
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qemu_irq handler)
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{
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if (line >= TC6393XB_GPIOS) {
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fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
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return;
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}
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s->handler[line] = handler;
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}
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static void tc6393xb_gpio_handler_update(TC6393xbState *s)
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{
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uint32_t level, diff;
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int bit;
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level = s->gpio_level & s->gpio_dir;
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for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
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bit = ffs(diff) - 1;
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qemu_set_irq(s->handler[bit], (level >> bit) & 1);
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}
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s->prev_level = level;
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}
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qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
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{
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return s->l3v;
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}
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static void tc6393xb_l3v(void *opaque, int line, int level)
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{
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TC6393xbState *s = opaque;
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s->blank = !level;
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fprintf(stderr, "L3V: %d\n", level);
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}
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static void tc6393xb_sub_irq(void *opaque, int line, int level) {
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TC6393xbState *s = opaque;
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uint8_t isr = s->scr.ISR;
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if (level)
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isr |= 1 << line;
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else
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isr &= ~(1 << line);
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s->scr.ISR = isr;
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qemu_set_irq(s->irq, isr & s->scr.IMR);
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}
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#define SCR_REG_B(N) \
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case SCR_ ##N: return s->scr.N
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#define SCR_REG_W(N) \
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case SCR_ ##N: return s->scr.N; \
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case SCR_ ##N + 1: return s->scr.N >> 8;
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#define SCR_REG_L(N) \
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case SCR_ ##N: return s->scr.N; \
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case SCR_ ##N + 1: return s->scr.N >> 8; \
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case SCR_ ##N + 2: return s->scr.N >> 16; \
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case SCR_ ##N + 3: return s->scr.N >> 24;
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#define SCR_REG_A(N) \
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case SCR_ ##N(0): return s->scr.N[0]; \
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case SCR_ ##N(1): return s->scr.N[1]; \
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case SCR_ ##N(2): return s->scr.N[2]
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static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
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{
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switch (addr) {
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case SCR_REVID:
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return 3;
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case SCR_REVID+1:
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return 0;
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SCR_REG_B(ISR);
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SCR_REG_B(IMR);
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SCR_REG_B(IRR);
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SCR_REG_W(GPER);
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SCR_REG_A(GPI_SR);
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SCR_REG_A(GPI_IMR);
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SCR_REG_A(GPI_EDER);
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SCR_REG_A(GPI_LIR);
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case SCR_GPO_DSR(0):
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case SCR_GPO_DSR(1):
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case SCR_GPO_DSR(2):
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return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
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case SCR_GPO_DOECR(0):
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case SCR_GPO_DOECR(1):
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case SCR_GPO_DOECR(2):
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return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
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SCR_REG_A(GP_IARCR);
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SCR_REG_A(GP_IARLCR);
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SCR_REG_A(GPI_BCR);
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SCR_REG_W(GPA_IARCR);
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SCR_REG_W(GPA_IARLCR);
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SCR_REG_W(CCR);
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SCR_REG_W(PLL2CR);
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SCR_REG_L(PLL1CR);
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SCR_REG_B(DIARCR);
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SCR_REG_B(DBOCR);
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SCR_REG_B(FER);
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SCR_REG_W(MCR);
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SCR_REG_B(CONFIG);
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SCR_REG_B(DEBUG);
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}
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fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
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return 0;
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}
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#undef SCR_REG_B
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#undef SCR_REG_W
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#undef SCR_REG_L
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#undef SCR_REG_A
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#define SCR_REG_B(N) \
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case SCR_ ##N: s->scr.N = value; return;
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#define SCR_REG_W(N) \
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case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
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case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
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#define SCR_REG_L(N) \
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case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
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case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \
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case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \
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case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
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#define SCR_REG_A(N) \
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case SCR_ ##N(0): s->scr.N[0] = value; return; \
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case SCR_ ##N(1): s->scr.N[1] = value; return; \
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case SCR_ ##N(2): s->scr.N[2] = value; return
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static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
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{
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switch (addr) {
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SCR_REG_B(ISR);
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SCR_REG_B(IMR);
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SCR_REG_B(IRR);
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SCR_REG_W(GPER);
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SCR_REG_A(GPI_SR);
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SCR_REG_A(GPI_IMR);
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SCR_REG_A(GPI_EDER);
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SCR_REG_A(GPI_LIR);
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case SCR_GPO_DSR(0):
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case SCR_GPO_DSR(1):
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case SCR_GPO_DSR(2):
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s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
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tc6393xb_gpio_handler_update(s);
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return;
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case SCR_GPO_DOECR(0):
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case SCR_GPO_DOECR(1):
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case SCR_GPO_DOECR(2):
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s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
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tc6393xb_gpio_handler_update(s);
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return;
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SCR_REG_A(GP_IARCR);
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SCR_REG_A(GP_IARLCR);
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SCR_REG_A(GPI_BCR);
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SCR_REG_W(GPA_IARCR);
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SCR_REG_W(GPA_IARLCR);
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SCR_REG_W(CCR);
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SCR_REG_W(PLL2CR);
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SCR_REG_L(PLL1CR);
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SCR_REG_B(DIARCR);
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SCR_REG_B(DBOCR);
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SCR_REG_B(FER);
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SCR_REG_W(MCR);
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SCR_REG_B(CONFIG);
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SCR_REG_B(DEBUG);
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}
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fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
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(uint32_t) addr, value & 0xff);
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}
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#undef SCR_REG_B
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#undef SCR_REG_W
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#undef SCR_REG_L
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#undef SCR_REG_A
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static void tc6393xb_nand_irq(TC6393xbState *s) {
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qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
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(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
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}
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static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
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switch (addr) {
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case NAND_CFG_COMMAND:
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return s->nand_enable ? 2 : 0;
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case NAND_CFG_BASE:
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case NAND_CFG_BASE + 1:
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case NAND_CFG_BASE + 2:
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case NAND_CFG_BASE + 3:
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return s->nand_phys >> (addr - NAND_CFG_BASE);
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}
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fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
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return 0;
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}
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static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
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switch (addr) {
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case NAND_CFG_COMMAND:
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s->nand_enable = (value & 0x2);
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return;
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case NAND_CFG_BASE:
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case NAND_CFG_BASE + 1:
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case NAND_CFG_BASE + 2:
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case NAND_CFG_BASE + 3:
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s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
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s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
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return;
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}
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fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
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(uint32_t) addr, value & 0xff);
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}
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static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
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switch (addr) {
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case NAND_DATA + 0:
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case NAND_DATA + 1:
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case NAND_DATA + 2:
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case NAND_DATA + 3:
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return nand_getio(s->flash);
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case NAND_MODE:
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return s->nand.mode;
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case NAND_STATUS:
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return 0x14;
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case NAND_ISR:
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return s->nand.isr;
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case NAND_IMR:
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return s->nand.imr;
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}
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fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
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return 0;
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}
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static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
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// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
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// (uint32_t) addr, value & 0xff);
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switch (addr) {
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case NAND_DATA + 0:
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case NAND_DATA + 1:
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case NAND_DATA + 2:
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case NAND_DATA + 3:
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nand_setio(s->flash, value);
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s->nand.isr |= 1;
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tc6393xb_nand_irq(s);
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return;
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case NAND_MODE:
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s->nand.mode = value;
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nand_setpins(s->flash,
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value & NAND_MODE_CLE,
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value & NAND_MODE_ALE,
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!(value & NAND_MODE_CE),
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value & NAND_MODE_WP,
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0); // FIXME: gnd
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switch (value & NAND_MODE_ECC_MASK) {
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case NAND_MODE_ECC_RST:
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ecc_reset(&s->ecc);
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break;
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case NAND_MODE_ECC_READ:
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// FIXME
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break;
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case NAND_MODE_ECC_EN:
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ecc_reset(&s->ecc);
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}
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return;
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case NAND_ISR:
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s->nand.isr = value;
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tc6393xb_nand_irq(s);
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return;
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case NAND_IMR:
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s->nand.imr = value;
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tc6393xb_nand_irq(s);
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return;
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}
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fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
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(uint32_t) addr, value & 0xff);
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}
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#define BITS 8
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#include "tc6393xb_template.h"
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#define BITS 15
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#include "tc6393xb_template.h"
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#define BITS 16
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#include "tc6393xb_template.h"
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#define BITS 24
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#include "tc6393xb_template.h"
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#define BITS 32
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#include "tc6393xb_template.h"
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static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
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{
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DisplaySurface *surface = qemu_console_surface(s->con);
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switch (surface_bits_per_pixel(surface)) {
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case 8:
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tc6393xb_draw_graphic8(s);
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break;
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case 15:
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tc6393xb_draw_graphic15(s);
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break;
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case 16:
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tc6393xb_draw_graphic16(s);
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break;
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case 24:
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tc6393xb_draw_graphic24(s);
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break;
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case 32:
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tc6393xb_draw_graphic32(s);
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break;
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default:
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printf("tc6393xb: unknown depth %d\n",
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surface_bits_per_pixel(surface));
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return;
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}
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dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
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}
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static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
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{
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DisplaySurface *surface = qemu_console_surface(s->con);
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int i, w;
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uint8_t *d;
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if (!full_update)
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return;
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w = s->scr_width * surface_bytes_per_pixel(surface);
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d = surface_data(surface);
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for(i = 0; i < s->scr_height; i++) {
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memset(d, 0, w);
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d += surface_stride(surface);
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}
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dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
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}
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static void tc6393xb_update_display(void *opaque)
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{
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TC6393xbState *s = opaque;
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DisplaySurface *surface = qemu_console_surface(s->con);
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int full_update;
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if (s->scr_width == 0 || s->scr_height == 0)
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return;
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full_update = 0;
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if (s->blanked != s->blank) {
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s->blanked = s->blank;
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full_update = 1;
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}
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if (s->scr_width != surface_width(surface) ||
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s->scr_height != surface_height(surface)) {
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qemu_console_resize(s->con, s->scr_width, s->scr_height);
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full_update = 1;
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}
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if (s->blanked)
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tc6393xb_draw_blank(s, full_update);
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else
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tc6393xb_draw_graphic(s, full_update);
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}
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static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
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unsigned size)
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{
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TC6393xbState *s = opaque;
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switch (addr >> 8) {
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case 0:
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return tc6393xb_scr_readb(s, addr & 0xff);
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case 1:
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return tc6393xb_nand_cfg_readb(s, addr & 0xff);
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};
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if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
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// return tc6393xb_nand_readb(s, addr & 0xff);
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uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
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// fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
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return d;
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}
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// fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
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return 0;
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}
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static void tc6393xb_writeb(void *opaque, hwaddr addr,
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uint64_t value, unsigned size) {
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TC6393xbState *s = opaque;
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switch (addr >> 8) {
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case 0:
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tc6393xb_scr_writeb(s, addr & 0xff, value);
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return;
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case 1:
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tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
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return;
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};
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if ((addr &~0xff) == s->nand_phys && s->nand_enable)
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tc6393xb_nand_writeb(s, addr & 0xff, value);
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else
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fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
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(uint32_t) addr, (int)value & 0xff);
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}
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TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
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{
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TC6393xbState *s;
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DriveInfo *nand;
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static const MemoryRegionOps tc6393xb_ops = {
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.read = tc6393xb_readb,
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.write = tc6393xb_writeb,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
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s->irq = irq;
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s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
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s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
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s->blanked = 1;
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s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
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nand = drive_get(IF_MTD, 0, 0);
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s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76);
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memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000);
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memory_region_add_subregion(sysmem, base, &s->iomem);
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memory_region_init_ram(&s->vram, "tc6393xb.vram", 0x100000);
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vmstate_register_ram_global(&s->vram);
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s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
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memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
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s->scr_width = 480;
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s->scr_height = 640;
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s->con = graphic_console_init(tc6393xb_update_display,
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NULL, /* invalidate */
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NULL, /* screen_dump */
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NULL, /* text_update */
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s);
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return s;
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}
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