qemu/target/ppc
Bin Meng 298091f831 target/ppc: Add E500 L2CSR0 write helper
Per EREF 2.0 [1] chapter 3.11.2:

The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core):

- L2FI  (L2 cache flash invalidate)
- L2FL  (L2 cache flush)
- L2LFC (L2 cache lock flash clear)

when set, a cache operation is initiated by hardware, and these bits
will be cleared when the operation is complete.

Since we don't model cache in QEMU, let's add a write helper to emulate
the cache operations completing instantly.

[1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREFRM.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Message-Id: <1612925152-20913-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-02-10 14:50:11 +11:00
..
translate
arch_dump.c
compat.c
cpu-models.c
cpu-models.h
cpu-param.h
cpu-qom.h
cpu.c
cpu.h target/ppc: Add E500 L2CSR0 write helper 2021-02-10 14:50:11 +11:00
dfp_helper.c
excp_helper.c
fpu_helper.c
gdbstub.c
helper_regs.h
helper.h
int_helper.c
internal.h
kvm_ppc.h
kvm-stub.c
kvm.c
machine.c
mem_helper.c
meson.build
mfrom_table_gen.c
mfrom_table.c.inc
misc_helper.c
mmu_helper.c
mmu-book3s-v3.c
mmu-book3s-v3.h
mmu-hash32.c
mmu-hash32.h
mmu-hash64.c
mmu-hash64.h
mmu-radix64.c
mmu-radix64.h
monitor.c
timebase_helper.c
trace-events
trace.h
translate_init.c.inc target/ppc: Add E500 L2CSR0 write helper 2021-02-10 14:50:11 +11:00
translate.c
user_only_helper.c